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    Searched refs:AVX (Results 1 - 9 of 9) sorted by null

  /external/lldb/tools/debugserver/source/MacOSX/i386/
DNBArchImplI386.h 67 typedef __i386_avx_state_t AVX;
99 e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
115 AVX avx; member in union:DNBArchImplI386::Context::__anon14368
DNBArchImplI386.cpp 355 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
356 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
357 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
358 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
359 m_state.context.fpu.avx.__fpu_ftw = 1;
360 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
361 m_state.context.fpu.avx.__fpu_fop = 2;
362 m_state.context.fpu.avx.__fpu_ip = 3;
363 m_state.context.fpu.avx.__fpu_cs = 4;
364 m_state.context.fpu.avx.__fpu_rsrv2 = 5
    [all...]
  /external/lldb/tools/debugserver/source/MacOSX/x86_64/
DNBArchImplX86_64.h 66 typedef __x86_64_avx_state_t AVX;
98 e_regSetWordSizeAVX = sizeof(AVX) / sizeof(int),
114 AVX avx; member in union:DNBArchImplX86_64::Context::__anon14386
DNBArchImplX86_64.cpp 86 // Only xnu-2020 or later has AVX support, any versions before
89 // verify the kernel version number manually or disable AVX support.
264 m_state.context.fpu.avx.__fpu_reserved[0] = -1;
265 m_state.context.fpu.avx.__fpu_reserved[1] = -1;
266 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fcw) = 0x1234;
267 *(uint16_t *)&(m_state.context.fpu.avx.__fpu_fsw) = 0x5678;
268 m_state.context.fpu.avx.__fpu_ftw = 1;
269 m_state.context.fpu.avx.__fpu_rsrv1 = UINT8_MAX;
270 m_state.context.fpu.avx.__fpu_fop = 2;
271 m_state.context.fpu.avx.__fpu_ip = 3
    [all...]
  /external/llvm/lib/Target/X86/
X86Subtarget.h 50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
203 /// Processor has AVX-512 PreFetch Instructions
206 /// Processor has AVX-512 Exponential and Reciprocal Instructions
209 /// Processor has AVX-512 Conflict Detection Instructions
212 /// Processor has AVX-512 Doubleword and Quadword instructions
215 /// Processor has AVX-512 Byte and Word instructions
218 /// Processor has AVX-512 Vector Length eXtenstions
334 bool hasAVX() const { return X86SSELevel >= AVX; }
  /external/libvpx/libvpx/third_party/libyuv/source/
x86inc.asm 605 %if cpuflag(AVX)
824 ; AVX abstraction layer
843 %error non-AVX emulation of ``%%opcode'' is not supported
897 ; 3arg AVX ops with a memory arg can only have it in src2,
1096 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
  /external/clang/lib/Basic/
Targets.cpp     [all...]
  /external/libvpx/libvpx/third_party/x86inc/
x86inc.asm 707 %if cpuflag(avx)
781 ; FIXME: INIT_AVX can be replaced by INIT_XMM avx
934 ; AVX abstraction layer
993 ; 3arg AVX ops with a memory arg can only have it in src2,
1184 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/third_party/x86inc/
x86inc.asm 686 %if cpuflag(avx)
760 ; FIXME: INIT_AVX can be replaced by INIT_XMM avx
913 ; AVX abstraction layer
972 ; 3arg AVX ops with a memory arg can only have it in src2,
1163 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN

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