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    Searched refs:AddrIdx (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCNaCl.h 20 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
MipsNaClELFStreamer.cpp 116 void sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx,
122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
149 unsigned AddrIdx;
151 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx)
162 sandboxLoadStoreStackChange(Inst, AddrIdx, STI, MaskBefore, MaskAfter);
202 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx,
223 *AddrIdx = 1;
234 *AddrIdx = 1;
242 *AddrIdx = 2
    [all...]
  /external/llvm/lib/Target/R600/
SILoadStoreOptimizer.cpp 175 int AddrIdx = AMDGPU::getNamedOperandIdx(I->getOpcode(), AMDGPU::OpName::addr);
176 const MachineOperand &AddrReg0 = I->getOperand(AddrIdx);
177 const MachineOperand &AddrReg1 = MBBI->getOperand(AddrIdx);
  /external/llvm/lib/Target/Mips/
MipsDelaySlotFiller.cpp 666 unsigned AddrIdx;
667 if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) &&
668 baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) ||

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