1 //===-- MipsDelaySlotFiller.cpp - Mips Delay Slot Filler ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Simple pass to fill delay slots with useful instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsMCNaCl.h" 15 #include "Mips.h" 16 #include "MipsInstrInfo.h" 17 #include "MipsTargetMachine.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/SmallPtrSet.h" 20 #include "llvm/ADT/Statistic.h" 21 #include "llvm/Analysis/AliasAnalysis.h" 22 #include "llvm/Analysis/ValueTracking.h" 23 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 26 #include "llvm/CodeGen/MachineRegisterInfo.h" 27 #include "llvm/CodeGen/PseudoSourceValue.h" 28 #include "llvm/Support/CommandLine.h" 29 #include "llvm/Target/TargetInstrInfo.h" 30 #include "llvm/Target/TargetMachine.h" 31 #include "llvm/Target/TargetRegisterInfo.h" 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "delay-slot-filler" 36 37 STATISTIC(FilledSlots, "Number of delay slots filled"); 38 STATISTIC(UsefulSlots, "Number of delay slots filled with instructions that" 39 " are not NOP."); 40 41 static cl::opt<bool> DisableDelaySlotFiller( 42 "disable-mips-delay-filler", 43 cl::init(false), 44 cl::desc("Fill all delay slots with NOPs."), 45 cl::Hidden); 46 47 static cl::opt<bool> DisableForwardSearch( 48 "disable-mips-df-forward-search", 49 cl::init(true), 50 cl::desc("Disallow MIPS delay filler to search forward."), 51 cl::Hidden); 52 53 static cl::opt<bool> DisableSuccBBSearch( 54 "disable-mips-df-succbb-search", 55 cl::init(true), 56 cl::desc("Disallow MIPS delay filler to search successor basic blocks."), 57 cl::Hidden); 58 59 static cl::opt<bool> DisableBackwardSearch( 60 "disable-mips-df-backward-search", 61 cl::init(false), 62 cl::desc("Disallow MIPS delay filler to search backward."), 63 cl::Hidden); 64 65 namespace { 66 typedef MachineBasicBlock::iterator Iter; 67 typedef MachineBasicBlock::reverse_iterator ReverseIter; 68 typedef SmallDenseMap<MachineBasicBlock*, MachineInstr*, 2> BB2BrMap; 69 70 class RegDefsUses { 71 public: 72 RegDefsUses(const TargetRegisterInfo &TRI); 73 void init(const MachineInstr &MI); 74 75 /// This function sets all caller-saved registers in Defs. 76 void setCallerSaved(const MachineInstr &MI); 77 78 /// This function sets all unallocatable registers in Defs. 79 void setUnallocatableRegs(const MachineFunction &MF); 80 81 /// Set bits in Uses corresponding to MBB's live-out registers except for 82 /// the registers that are live-in to SuccBB. 83 void addLiveOut(const MachineBasicBlock &MBB, 84 const MachineBasicBlock &SuccBB); 85 86 bool update(const MachineInstr &MI, unsigned Begin, unsigned End); 87 88 private: 89 bool checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, unsigned Reg, 90 bool IsDef) const; 91 92 /// Returns true if Reg or its alias is in RegSet. 93 bool isRegInSet(const BitVector &RegSet, unsigned Reg) const; 94 95 const TargetRegisterInfo &TRI; 96 BitVector Defs, Uses; 97 }; 98 99 /// Base class for inspecting loads and stores. 100 class InspectMemInstr { 101 public: 102 InspectMemInstr(bool ForbidMemInstr_) 103 : OrigSeenLoad(false), OrigSeenStore(false), SeenLoad(false), 104 SeenStore(false), ForbidMemInstr(ForbidMemInstr_) {} 105 106 /// Return true if MI cannot be moved to delay slot. 107 bool hasHazard(const MachineInstr &MI); 108 109 virtual ~InspectMemInstr() {} 110 111 protected: 112 /// Flags indicating whether loads or stores have been seen. 113 bool OrigSeenLoad, OrigSeenStore, SeenLoad, SeenStore; 114 115 /// Memory instructions are not allowed to move to delay slot if this flag 116 /// is true. 117 bool ForbidMemInstr; 118 119 private: 120 virtual bool hasHazard_(const MachineInstr &MI) = 0; 121 }; 122 123 /// This subclass rejects any memory instructions. 124 class NoMemInstr : public InspectMemInstr { 125 public: 126 NoMemInstr() : InspectMemInstr(true) {} 127 private: 128 bool hasHazard_(const MachineInstr &MI) override { return true; } 129 }; 130 131 /// This subclass accepts loads from stacks and constant loads. 132 class LoadFromStackOrConst : public InspectMemInstr { 133 public: 134 LoadFromStackOrConst() : InspectMemInstr(false) {} 135 private: 136 bool hasHazard_(const MachineInstr &MI) override; 137 }; 138 139 /// This subclass uses memory dependence information to determine whether a 140 /// memory instruction can be moved to a delay slot. 141 class MemDefsUses : public InspectMemInstr { 142 public: 143 MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI); 144 145 private: 146 typedef PointerUnion<const Value *, const PseudoSourceValue *> ValueType; 147 148 bool hasHazard_(const MachineInstr &MI) override; 149 150 /// Update Defs and Uses. Return true if there exist dependences that 151 /// disqualify the delay slot candidate between V and values in Uses and 152 /// Defs. 153 bool updateDefsUses(ValueType V, bool MayStore); 154 155 /// Get the list of underlying objects of MI's memory operand. 156 bool getUnderlyingObjects(const MachineInstr &MI, 157 SmallVectorImpl<ValueType> &Objects) const; 158 159 const MachineFrameInfo *MFI; 160 SmallPtrSet<ValueType, 4> Uses, Defs; 161 const DataLayout &DL; 162 163 /// Flags indicating whether loads or stores with no underlying objects have 164 /// been seen. 165 bool SeenNoObjLoad, SeenNoObjStore; 166 }; 167 168 class Filler : public MachineFunctionPass { 169 public: 170 Filler(TargetMachine &tm) 171 : MachineFunctionPass(ID), TM(tm) { } 172 173 const char *getPassName() const override { 174 return "Mips Delay Slot Filler"; 175 } 176 177 bool runOnMachineFunction(MachineFunction &F) override { 178 bool Changed = false; 179 for (MachineFunction::iterator FI = F.begin(), FE = F.end(); 180 FI != FE; ++FI) 181 Changed |= runOnMachineBasicBlock(*FI); 182 183 // This pass invalidates liveness information when it reorders 184 // instructions to fill delay slot. Without this, -verify-machineinstrs 185 // will fail. 186 if (Changed) 187 F.getRegInfo().invalidateLiveness(); 188 189 return Changed; 190 } 191 192 void getAnalysisUsage(AnalysisUsage &AU) const override { 193 AU.addRequired<MachineBranchProbabilityInfo>(); 194 MachineFunctionPass::getAnalysisUsage(AU); 195 } 196 197 private: 198 bool runOnMachineBasicBlock(MachineBasicBlock &MBB); 199 200 Iter replaceWithCompactBranch(MachineBasicBlock &MBB, 201 Iter Branch, DebugLoc DL); 202 203 Iter replaceWithCompactJump(MachineBasicBlock &MBB, 204 Iter Jump, DebugLoc DL); 205 206 /// This function checks if it is valid to move Candidate to the delay slot 207 /// and returns true if it isn't. It also updates memory and register 208 /// dependence information. 209 bool delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU, 210 InspectMemInstr &IM) const; 211 212 /// This function searches range [Begin, End) for an instruction that can be 213 /// moved to the delay slot. Returns true on success. 214 template<typename IterTy> 215 bool searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, 216 RegDefsUses &RegDU, InspectMemInstr &IM, Iter Slot, 217 IterTy &Filler) const; 218 219 /// This function searches in the backward direction for an instruction that 220 /// can be moved to the delay slot. Returns true on success. 221 bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const; 222 223 /// This function searches MBB in the forward direction for an instruction 224 /// that can be moved to the delay slot. Returns true on success. 225 bool searchForward(MachineBasicBlock &MBB, Iter Slot) const; 226 227 /// This function searches one of MBB's successor blocks for an instruction 228 /// that can be moved to the delay slot and inserts clones of the 229 /// instruction into the successor's predecessor blocks. 230 bool searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const; 231 232 /// Pick a successor block of MBB. Return NULL if MBB doesn't have a 233 /// successor block that is not a landing pad. 234 MachineBasicBlock *selectSuccBB(MachineBasicBlock &B) const; 235 236 /// This function analyzes MBB and returns an instruction with an unoccupied 237 /// slot that branches to Dst. 238 std::pair<MipsInstrInfo::BranchType, MachineInstr *> 239 getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const; 240 241 /// Examine Pred and see if it is possible to insert an instruction into 242 /// one of its branches delay slot or its end. 243 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 244 RegDefsUses &RegDU, bool &HasMultipleSuccs, 245 BB2BrMap &BrMap) const; 246 247 bool terminateSearch(const MachineInstr &Candidate) const; 248 249 TargetMachine &TM; 250 251 static char ID; 252 }; 253 char Filler::ID = 0; 254 } // end of anonymous namespace 255 256 static bool hasUnoccupiedSlot(const MachineInstr *MI) { 257 return MI->hasDelaySlot() && !MI->isBundledWithSucc(); 258 } 259 260 /// This function inserts clones of Filler into predecessor blocks. 261 static void insertDelayFiller(Iter Filler, const BB2BrMap &BrMap) { 262 MachineFunction *MF = Filler->getParent()->getParent(); 263 264 for (BB2BrMap::const_iterator I = BrMap.begin(); I != BrMap.end(); ++I) { 265 if (I->second) { 266 MIBundleBuilder(I->second).append(MF->CloneMachineInstr(&*Filler)); 267 ++UsefulSlots; 268 } else { 269 I->first->insert(I->first->end(), MF->CloneMachineInstr(&*Filler)); 270 } 271 } 272 } 273 274 /// This function adds registers Filler defines to MBB's live-in register list. 275 static void addLiveInRegs(Iter Filler, MachineBasicBlock &MBB) { 276 for (unsigned I = 0, E = Filler->getNumOperands(); I != E; ++I) { 277 const MachineOperand &MO = Filler->getOperand(I); 278 unsigned R; 279 280 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg())) 281 continue; 282 283 #ifndef NDEBUG 284 const MachineFunction &MF = *MBB.getParent(); 285 assert(MF.getSubtarget().getRegisterInfo()->getAllocatableSet(MF).test(R) && 286 "Shouldn't move an instruction with unallocatable registers across " 287 "basic block boundaries."); 288 #endif 289 290 if (!MBB.isLiveIn(R)) 291 MBB.addLiveIn(R); 292 } 293 } 294 295 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI) 296 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} 297 298 void RegDefsUses::init(const MachineInstr &MI) { 299 // Add all register operands which are explicit and non-variadic. 300 update(MI, 0, MI.getDesc().getNumOperands()); 301 302 // If MI is a call, add RA to Defs to prevent users of RA from going into 303 // delay slot. 304 if (MI.isCall()) 305 Defs.set(Mips::RA); 306 307 // Add all implicit register operands of branch instructions except 308 // register AT. 309 if (MI.isBranch()) { 310 update(MI, MI.getDesc().getNumOperands(), MI.getNumOperands()); 311 Defs.reset(Mips::AT); 312 } 313 } 314 315 void RegDefsUses::setCallerSaved(const MachineInstr &MI) { 316 assert(MI.isCall()); 317 318 // If MI is a call, add all caller-saved registers to Defs. 319 BitVector CallerSavedRegs(TRI.getNumRegs(), true); 320 321 CallerSavedRegs.reset(Mips::ZERO); 322 CallerSavedRegs.reset(Mips::ZERO_64); 323 324 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(MI.getParent()->getParent()); 325 *R; ++R) 326 for (MCRegAliasIterator AI(*R, &TRI, true); AI.isValid(); ++AI) 327 CallerSavedRegs.reset(*AI); 328 329 Defs |= CallerSavedRegs; 330 } 331 332 void RegDefsUses::setUnallocatableRegs(const MachineFunction &MF) { 333 BitVector AllocSet = TRI.getAllocatableSet(MF); 334 335 for (int R = AllocSet.find_first(); R != -1; R = AllocSet.find_next(R)) 336 for (MCRegAliasIterator AI(R, &TRI, false); AI.isValid(); ++AI) 337 AllocSet.set(*AI); 338 339 AllocSet.set(Mips::ZERO); 340 AllocSet.set(Mips::ZERO_64); 341 342 Defs |= AllocSet.flip(); 343 } 344 345 void RegDefsUses::addLiveOut(const MachineBasicBlock &MBB, 346 const MachineBasicBlock &SuccBB) { 347 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), 348 SE = MBB.succ_end(); SI != SE; ++SI) 349 if (*SI != &SuccBB) 350 for (MachineBasicBlock::livein_iterator LI = (*SI)->livein_begin(), 351 LE = (*SI)->livein_end(); LI != LE; ++LI) 352 Uses.set(*LI); 353 } 354 355 bool RegDefsUses::update(const MachineInstr &MI, unsigned Begin, unsigned End) { 356 BitVector NewDefs(TRI.getNumRegs()), NewUses(TRI.getNumRegs()); 357 bool HasHazard = false; 358 359 for (unsigned I = Begin; I != End; ++I) { 360 const MachineOperand &MO = MI.getOperand(I); 361 362 if (MO.isReg() && MO.getReg()) 363 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef()); 364 } 365 366 Defs |= NewDefs; 367 Uses |= NewUses; 368 369 return HasHazard; 370 } 371 372 bool RegDefsUses::checkRegDefsUses(BitVector &NewDefs, BitVector &NewUses, 373 unsigned Reg, bool IsDef) const { 374 if (IsDef) { 375 NewDefs.set(Reg); 376 // check whether Reg has already been defined or used. 377 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); 378 } 379 380 NewUses.set(Reg); 381 // check whether Reg has already been defined. 382 return isRegInSet(Defs, Reg); 383 } 384 385 bool RegDefsUses::isRegInSet(const BitVector &RegSet, unsigned Reg) const { 386 // Check Reg and all aliased Registers. 387 for (MCRegAliasIterator AI(Reg, &TRI, true); AI.isValid(); ++AI) 388 if (RegSet.test(*AI)) 389 return true; 390 return false; 391 } 392 393 bool InspectMemInstr::hasHazard(const MachineInstr &MI) { 394 if (!MI.mayStore() && !MI.mayLoad()) 395 return false; 396 397 if (ForbidMemInstr) 398 return true; 399 400 OrigSeenLoad = SeenLoad; 401 OrigSeenStore = SeenStore; 402 SeenLoad |= MI.mayLoad(); 403 SeenStore |= MI.mayStore(); 404 405 // If MI is an ordered or volatile memory reference, disallow moving 406 // subsequent loads and stores to delay slot. 407 if (MI.hasOrderedMemoryRef() && (OrigSeenLoad || OrigSeenStore)) { 408 ForbidMemInstr = true; 409 return true; 410 } 411 412 return hasHazard_(MI); 413 } 414 415 bool LoadFromStackOrConst::hasHazard_(const MachineInstr &MI) { 416 if (MI.mayStore()) 417 return true; 418 419 if (!MI.hasOneMemOperand() || !(*MI.memoperands_begin())->getPseudoValue()) 420 return true; 421 422 if (const PseudoSourceValue *PSV = 423 (*MI.memoperands_begin())->getPseudoValue()) { 424 if (isa<FixedStackPseudoSourceValue>(PSV)) 425 return false; 426 return !PSV->isConstant(nullptr) && PSV != PseudoSourceValue::getStack(); 427 } 428 429 return true; 430 } 431 432 MemDefsUses::MemDefsUses(const DataLayout &DL, const MachineFrameInfo *MFI_) 433 : InspectMemInstr(false), MFI(MFI_), DL(DL), SeenNoObjLoad(false), 434 SeenNoObjStore(false) {} 435 436 bool MemDefsUses::hasHazard_(const MachineInstr &MI) { 437 bool HasHazard = false; 438 SmallVector<ValueType, 4> Objs; 439 440 // Check underlying object list. 441 if (getUnderlyingObjects(MI, Objs)) { 442 for (SmallVectorImpl<ValueType>::const_iterator I = Objs.begin(); 443 I != Objs.end(); ++I) 444 HasHazard |= updateDefsUses(*I, MI.mayStore()); 445 446 return HasHazard; 447 } 448 449 // No underlying objects found. 450 HasHazard = MI.mayStore() && (OrigSeenLoad || OrigSeenStore); 451 HasHazard |= MI.mayLoad() || OrigSeenStore; 452 453 SeenNoObjLoad |= MI.mayLoad(); 454 SeenNoObjStore |= MI.mayStore(); 455 456 return HasHazard; 457 } 458 459 bool MemDefsUses::updateDefsUses(ValueType V, bool MayStore) { 460 if (MayStore) 461 return !Defs.insert(V).second || Uses.count(V) || SeenNoObjStore || 462 SeenNoObjLoad; 463 464 Uses.insert(V); 465 return Defs.count(V) || SeenNoObjStore; 466 } 467 468 bool MemDefsUses:: 469 getUnderlyingObjects(const MachineInstr &MI, 470 SmallVectorImpl<ValueType> &Objects) const { 471 if (!MI.hasOneMemOperand() || 472 (!(*MI.memoperands_begin())->getValue() && 473 !(*MI.memoperands_begin())->getPseudoValue())) 474 return false; 475 476 if (const PseudoSourceValue *PSV = 477 (*MI.memoperands_begin())->getPseudoValue()) { 478 if (!PSV->isAliased(MFI)) 479 return false; 480 Objects.push_back(PSV); 481 return true; 482 } 483 484 const Value *V = (*MI.memoperands_begin())->getValue(); 485 486 SmallVector<Value *, 4> Objs; 487 GetUnderlyingObjects(const_cast<Value *>(V), Objs, DL); 488 489 for (SmallVectorImpl<Value *>::iterator I = Objs.begin(), E = Objs.end(); 490 I != E; ++I) { 491 if (!isIdentifiedObject(V)) 492 return false; 493 494 Objects.push_back(*I); 495 } 496 497 return true; 498 } 499 500 // Replace Branch with the compact branch instruction. 501 Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB, 502 Iter Branch, DebugLoc DL) { 503 const MipsInstrInfo *TII = 504 MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo(); 505 506 unsigned NewOpcode = 507 (((unsigned) Branch->getOpcode()) == Mips::BEQ) ? Mips::BEQZC_MM 508 : Mips::BNEZC_MM; 509 510 const MCInstrDesc &NewDesc = TII->get(NewOpcode); 511 MachineInstrBuilder MIB = BuildMI(MBB, Branch, DL, NewDesc); 512 513 MIB.addReg(Branch->getOperand(0).getReg()); 514 MIB.addMBB(Branch->getOperand(2).getMBB()); 515 516 Iter tmpIter = Branch; 517 Branch = std::prev(Branch); 518 MBB.erase(tmpIter); 519 520 return Branch; 521 } 522 523 // Replace Jumps with the compact jump instruction. 524 Iter Filler::replaceWithCompactJump(MachineBasicBlock &MBB, 525 Iter Jump, DebugLoc DL) { 526 const MipsInstrInfo *TII = 527 MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo(); 528 529 const MCInstrDesc &NewDesc = TII->get(Mips::JRC16_MM); 530 MachineInstrBuilder MIB = BuildMI(MBB, Jump, DL, NewDesc); 531 532 MIB.addReg(Jump->getOperand(0).getReg()); 533 534 Iter tmpIter = Jump; 535 Jump = std::prev(Jump); 536 MBB.erase(tmpIter); 537 538 return Jump; 539 } 540 541 // For given opcode returns opcode of corresponding instruction with short 542 // delay slot. 543 static int getEquivalentCallShort(int Opcode) { 544 switch (Opcode) { 545 case Mips::BGEZAL: 546 return Mips::BGEZALS_MM; 547 case Mips::BLTZAL: 548 return Mips::BLTZALS_MM; 549 case Mips::JAL: 550 return Mips::JALS_MM; 551 case Mips::JALR: 552 return Mips::JALRS_MM; 553 case Mips::JALR16_MM: 554 return Mips::JALRS16_MM; 555 default: 556 llvm_unreachable("Unexpected call instruction for microMIPS."); 557 } 558 } 559 560 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block. 561 /// We assume there is only one delay slot per delayed instruction. 562 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { 563 bool Changed = false; 564 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 565 bool InMicroMipsMode = STI.inMicroMipsMode(); 566 const MipsInstrInfo *TII = STI.getInstrInfo(); 567 568 for (Iter I = MBB.begin(); I != MBB.end(); ++I) { 569 if (!hasUnoccupiedSlot(&*I)) 570 continue; 571 572 ++FilledSlots; 573 Changed = true; 574 575 // Delay slot filling is disabled at -O0. 576 if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) { 577 bool Filled = false; 578 579 if (searchBackward(MBB, I)) { 580 Filled = true; 581 } else if (I->isTerminator()) { 582 if (searchSuccBBs(MBB, I)) { 583 Filled = true; 584 } 585 } else if (searchForward(MBB, I)) { 586 Filled = true; 587 } 588 589 if (Filled) { 590 // Get instruction with delay slot. 591 MachineBasicBlock::instr_iterator DSI(I); 592 593 if (InMicroMipsMode && TII->GetInstSizeInBytes(std::next(DSI)) == 2 && 594 DSI->isCall()) { 595 // If instruction in delay slot is 16b change opcode to 596 // corresponding instruction with short delay slot. 597 DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); 598 } 599 600 continue; 601 } 602 } 603 604 // If instruction is BEQ or BNE with one ZERO register, then instead of 605 // adding NOP replace this instruction with the corresponding compact 606 // branch instruction, i.e. BEQZC or BNEZC. 607 unsigned Opcode = I->getOpcode(); 608 if (InMicroMipsMode) { 609 switch (Opcode) { 610 case Mips::BEQ: 611 case Mips::BNE: 612 if (((unsigned) I->getOperand(1).getReg()) == Mips::ZERO) { 613 I = replaceWithCompactBranch(MBB, I, I->getDebugLoc()); 614 continue; 615 } 616 break; 617 case Mips::JR: 618 case Mips::PseudoReturn: 619 case Mips::PseudoIndirectBranch: 620 // For microMIPS the PseudoReturn and PseudoIndirectBranch are allways 621 // expanded to JR_MM, so they can be replaced with JRC16_MM. 622 I = replaceWithCompactJump(MBB, I, I->getDebugLoc()); 623 continue; 624 default: 625 break; 626 } 627 } 628 // Bundle the NOP to the instruction with the delay slot. 629 BuildMI(MBB, std::next(I), I->getDebugLoc(), TII->get(Mips::NOP)); 630 MIBundleBuilder(MBB, I, std::next(I, 2)); 631 } 632 633 return Changed; 634 } 635 636 /// createMipsDelaySlotFillerPass - Returns a pass that fills in delay 637 /// slots in Mips MachineFunctions 638 FunctionPass *llvm::createMipsDelaySlotFillerPass(MipsTargetMachine &tm) { 639 return new Filler(tm); 640 } 641 642 template<typename IterTy> 643 bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, 644 RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot, 645 IterTy &Filler) const { 646 for (IterTy I = Begin; I != End; ++I) { 647 // skip debug value 648 if (I->isDebugValue()) 649 continue; 650 651 if (terminateSearch(*I)) 652 break; 653 654 assert((!I->isCall() && !I->isReturn() && !I->isBranch()) && 655 "Cannot put calls, returns or branches in delay slot."); 656 657 if (delayHasHazard(*I, RegDU, IM)) 658 continue; 659 660 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>(); 661 if (STI.isTargetNaCl()) { 662 // In NaCl, instructions that must be masked are forbidden in delay slots. 663 // We only check for loads, stores and SP changes. Calls, returns and 664 // branches are not checked because non-NaCl targets never put them in 665 // delay slots. 666 unsigned AddrIdx; 667 if ((isBasePlusOffsetMemoryAccess(I->getOpcode(), &AddrIdx) && 668 baseRegNeedsLoadStoreMask(I->getOperand(AddrIdx).getReg())) || 669 I->modifiesRegister(Mips::SP, STI.getRegisterInfo())) 670 continue; 671 } 672 673 bool InMicroMipsMode = STI.inMicroMipsMode(); 674 const MipsInstrInfo *TII = STI.getInstrInfo(); 675 unsigned Opcode = (*Slot).getOpcode(); 676 if (InMicroMipsMode && TII->GetInstSizeInBytes(&(*I)) == 2 && 677 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || 678 Opcode == Mips::PseudoReturn)) 679 continue; 680 681 Filler = I; 682 return true; 683 } 684 685 return false; 686 } 687 688 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const { 689 if (DisableBackwardSearch) 690 return false; 691 692 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 693 MemDefsUses MemDU(*TM.getDataLayout(), MBB.getParent()->getFrameInfo()); 694 ReverseIter Filler; 695 696 RegDU.init(*Slot); 697 698 if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Slot, 699 Filler)) 700 return false; 701 702 MBB.splice(std::next(Slot), &MBB, std::next(Filler).base()); 703 MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); 704 ++UsefulSlots; 705 return true; 706 } 707 708 bool Filler::searchForward(MachineBasicBlock &MBB, Iter Slot) const { 709 // Can handle only calls. 710 if (DisableForwardSearch || !Slot->isCall()) 711 return false; 712 713 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 714 NoMemInstr NM; 715 Iter Filler; 716 717 RegDU.setCallerSaved(*Slot); 718 719 if (!searchRange(MBB, std::next(Slot), MBB.end(), RegDU, NM, Slot, Filler)) 720 return false; 721 722 MBB.splice(std::next(Slot), &MBB, Filler); 723 MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); 724 ++UsefulSlots; 725 return true; 726 } 727 728 bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const { 729 if (DisableSuccBBSearch) 730 return false; 731 732 MachineBasicBlock *SuccBB = selectSuccBB(MBB); 733 734 if (!SuccBB) 735 return false; 736 737 RegDefsUses RegDU(*MBB.getParent()->getSubtarget().getRegisterInfo()); 738 bool HasMultipleSuccs = false; 739 BB2BrMap BrMap; 740 std::unique_ptr<InspectMemInstr> IM; 741 Iter Filler; 742 743 // Iterate over SuccBB's predecessor list. 744 for (MachineBasicBlock::pred_iterator PI = SuccBB->pred_begin(), 745 PE = SuccBB->pred_end(); PI != PE; ++PI) 746 if (!examinePred(**PI, *SuccBB, RegDU, HasMultipleSuccs, BrMap)) 747 return false; 748 749 // Do not allow moving instructions which have unallocatable register operands 750 // across basic block boundaries. 751 RegDU.setUnallocatableRegs(*MBB.getParent()); 752 753 // Only allow moving loads from stack or constants if any of the SuccBB's 754 // predecessors have multiple successors. 755 if (HasMultipleSuccs) { 756 IM.reset(new LoadFromStackOrConst()); 757 } else { 758 const MachineFrameInfo *MFI = MBB.getParent()->getFrameInfo(); 759 IM.reset(new MemDefsUses(*TM.getDataLayout(), MFI)); 760 } 761 762 if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot, 763 Filler)) 764 return false; 765 766 insertDelayFiller(Filler, BrMap); 767 addLiveInRegs(Filler, *SuccBB); 768 Filler->eraseFromParent(); 769 770 return true; 771 } 772 773 MachineBasicBlock *Filler::selectSuccBB(MachineBasicBlock &B) const { 774 if (B.succ_empty()) 775 return nullptr; 776 777 // Select the successor with the larget edge weight. 778 auto &Prob = getAnalysis<MachineBranchProbabilityInfo>(); 779 MachineBasicBlock *S = *std::max_element(B.succ_begin(), B.succ_end(), 780 [&](const MachineBasicBlock *Dst0, 781 const MachineBasicBlock *Dst1) { 782 return Prob.getEdgeWeight(&B, Dst0) < Prob.getEdgeWeight(&B, Dst1); 783 }); 784 return S->isLandingPad() ? nullptr : S; 785 } 786 787 std::pair<MipsInstrInfo::BranchType, MachineInstr *> 788 Filler::getBranch(MachineBasicBlock &MBB, const MachineBasicBlock &Dst) const { 789 const MipsInstrInfo *TII = 790 MBB.getParent()->getSubtarget<MipsSubtarget>().getInstrInfo(); 791 MachineBasicBlock *TrueBB = nullptr, *FalseBB = nullptr; 792 SmallVector<MachineInstr*, 2> BranchInstrs; 793 SmallVector<MachineOperand, 2> Cond; 794 795 MipsInstrInfo::BranchType R = 796 TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs); 797 798 if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch)) 799 return std::make_pair(R, nullptr); 800 801 if (R != MipsInstrInfo::BT_CondUncond) { 802 if (!hasUnoccupiedSlot(BranchInstrs[0])) 803 return std::make_pair(MipsInstrInfo::BT_None, nullptr); 804 805 assert(((R != MipsInstrInfo::BT_Uncond) || (TrueBB == &Dst))); 806 807 return std::make_pair(R, BranchInstrs[0]); 808 } 809 810 assert((TrueBB == &Dst) || (FalseBB == &Dst)); 811 812 // Examine the conditional branch. See if its slot is occupied. 813 if (hasUnoccupiedSlot(BranchInstrs[0])) 814 return std::make_pair(MipsInstrInfo::BT_Cond, BranchInstrs[0]); 815 816 // If that fails, try the unconditional branch. 817 if (hasUnoccupiedSlot(BranchInstrs[1]) && (FalseBB == &Dst)) 818 return std::make_pair(MipsInstrInfo::BT_Uncond, BranchInstrs[1]); 819 820 return std::make_pair(MipsInstrInfo::BT_None, nullptr); 821 } 822 823 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 824 RegDefsUses &RegDU, bool &HasMultipleSuccs, 825 BB2BrMap &BrMap) const { 826 std::pair<MipsInstrInfo::BranchType, MachineInstr *> P = 827 getBranch(Pred, Succ); 828 829 // Return if either getBranch wasn't able to analyze the branches or there 830 // were no branches with unoccupied slots. 831 if (P.first == MipsInstrInfo::BT_None) 832 return false; 833 834 if ((P.first != MipsInstrInfo::BT_Uncond) && 835 (P.first != MipsInstrInfo::BT_NoBranch)) { 836 HasMultipleSuccs = true; 837 RegDU.addLiveOut(Pred, Succ); 838 } 839 840 BrMap[&Pred] = P.second; 841 return true; 842 } 843 844 bool Filler::delayHasHazard(const MachineInstr &Candidate, RegDefsUses &RegDU, 845 InspectMemInstr &IM) const { 846 bool HasHazard = (Candidate.isImplicitDef() || Candidate.isKill()); 847 848 HasHazard |= IM.hasHazard(Candidate); 849 HasHazard |= RegDU.update(Candidate, 0, Candidate.getNumOperands()); 850 851 return HasHazard; 852 } 853 854 bool Filler::terminateSearch(const MachineInstr &Candidate) const { 855 return (Candidate.isTerminator() || Candidate.isCall() || 856 Candidate.isPosition() || Candidate.isInlineAsm() || 857 Candidate.hasUnmodeledSideEffects()); 858 } 859