| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen7_cc_state.c | 45 .brw = BRW_NEW_BATCH,
65 .brw = BRW_NEW_BATCH,
85 .brw = BRW_NEW_BATCH,
|
| gen6_sampler_state.c | 53 .brw = (BRW_NEW_BATCH |
|
| gen6_viewport_state.c | 61 .brw = BRW_NEW_BATCH,
104 .brw = BRW_NEW_BATCH,
128 .brw = (BRW_NEW_BATCH |
|
| gen7_viewport_state.c | 78 .brw = BRW_NEW_BATCH,
99 .brw = BRW_NEW_BATCH,
|
| brw_vs_surface_state.c | 108 .brw = (BRW_NEW_BATCH | BRW_NEW_VERTEX_PROGRAM),
132 .brw = BRW_NEW_BATCH,
177 .brw = (BRW_NEW_BATCH |
|
| gen6_sol.c | 72 .brw = (BRW_NEW_BATCH |
125 .brw = (BRW_NEW_BATCH |
149 .brw = (BRW_NEW_BATCH |
|
| brw_gs_state.c | 92 .brw = (BRW_NEW_BATCH |
|
| gen6_scissor_state.c | 91 .brw = BRW_NEW_BATCH,
|
| gen7_disable.c | 130 .brw = BRW_NEW_BATCH,
|
| gen6_vs_state.c | 123 .brw = (BRW_NEW_BATCH |
233 BRW_NEW_BATCH),
|
| gen7_wm_state.c | 106 BRW_NEW_BATCH),
236 BRW_NEW_BATCH),
|
| gen7_vs_state.c | 116 BRW_NEW_BATCH),
|
| gen6_cc.c | 204 .brw = BRW_NEW_BATCH,
240 .brw = BRW_NEW_BATCH,
261 .brw = (BRW_NEW_BATCH |
|
| brw_clip_state.c | 121 .brw = (BRW_NEW_BATCH |
|
| brw_vs_state.c | 172 .brw = (BRW_NEW_BATCH |
|
| gen6_depthstencil.c | 97 .brw = BRW_NEW_BATCH,
|
| brw_cc.c | 65 .brw = BRW_NEW_BATCH,
233 .brw = BRW_NEW_BATCH,
|
| brw_sf_state.c | 121 .brw = BRW_NEW_BATCH,
325 .brw = (BRW_NEW_BATCH |
|
| gen6_wm_state.c | 85 .brw = (BRW_NEW_BATCH |
238 BRW_NEW_BATCH),
|
| brw_misc_state.c | 93 .brw = (BRW_NEW_BATCH |
129 .brw = (BRW_NEW_BATCH |
189 BRW_NEW_BATCH |
598 .brw = BRW_NEW_BATCH,
939 .brw = (BRW_NEW_BATCH |
|
| brw_vtbl.c | 171 static void brw_new_batch( struct intel_context *intel ) function
184 brw->state.dirty.brw |= BRW_NEW_BATCH;
243 brw->intel.vtbl.new_batch = brw_new_batch;
|
| gen7_misc_state.c | 285 .brw = BRW_NEW_BATCH,
|
| brw_wm_state.c | 258 .brw = (BRW_NEW_BATCH |
|
| gen7_sampler_state.c | 223 .brw = BRW_NEW_BATCH |
|
| gen7_sol_state.c | 264 .brw = (BRW_NEW_BATCH |
|
