| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILNIDevice.cpp | 65 mHWBits.set(AMDGPUDeviceInfo::FMA);
|
| AMDILEvergreenDevice.cpp | 133 mHWBits.set(AMDGPUDeviceInfo::FMA);
147 mSWBits.set(AMDGPUDeviceInfo::FMA);
164 mSWBits.set(AMDGPUDeviceInfo::FMA);
|
| AMDILDeviceInfo.h | 46 FMA = 0xC, // Use HW FMA or SW FMA.
|
| AMDIL7XXDevice.cpp | 104 mSWBits.set(AMDGPUDeviceInfo::FMA);
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 234 /// FMA - Perform a * b + c with no intermediate rounding step.
235 FMA,
[all...] |
| BasicTTIImpl.h | 616 case Intrinsic::fma:
617 ISD = ISD::FMA;
620 ISD = ISD::FMA;
653 // If we can't lower fmuladd into an FMA estimate the cost as a floating
|
| /external/llvm/test/tools/llvm-readobj/ARM/ |
| attribute-2.s | 37 @CHECK-OBJ-NEXT: Description: NEONv2+FMA
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| rtl.def | 719 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
[all...] |
| genrtl.h | 1135 gen_rtx_fmt_eee (FMA, (MODE), (ARG0), (ARG1), (ARG2))
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 620 // This currently forces unfolding various combinations of fsub into fma with
621 // free fneg'd operands. As long as we have fast FMA (controlled by
624 // When fma is quarter rate, for f64 where add / sub are at best half rate,
642 // have different rates for fma or all f64 operations.
653 // however does not support denormals, so we do report fma as faster if we have
654 // a fast fma device and require denormals.
666 // which we should prefer over fma. We can't use this if we want to support
[all...] |
| AMDGPUISelLowering.cpp | 374 setOperationAction(ISD::FMA, VT, Expand);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 190 case ISD::FMA: return "fma";
|
| DAGCombiner.cpp | [all...] |
| LegalizeVectorOps.cpp | 319 case ISD::FMA:
[all...] |
| LegalizeFloatTypes.cpp | 84 case ISD::FMA: R = SoftenFloatRes_FMA(N); break;
[all...] |
| LegalizeVectorTypes.cpp | 128 case ISD::FMA:
673 case ISD::FMA:
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 279 setOperationAction(ISD::FMA, MVT::f32, Legal);
280 setOperationAction(ISD::FMA, MVT::f64, Legal);
281 setOperationAction(ISD::FMA, MVT::f128, Expand);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 315 setOperationAction(ISD::FMA, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 351 setOperationAction(ISD::FMA, MVT::f32, Expand);
352 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 167 setOperationAction(ISD::FMA , MVT::f64, Legal);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
555 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 614 // We don't support FMA.
615 setOperationAction(ISD::FMA, MVT::f64, Expand);
616 setOperationAction(ISD::FMA, MVT::f32, Expand);
649 setOperationAction(ISD::FMA, MVT::f80, Expand);
693 setOperationAction(ISD::FMA, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 167 setOperationAction(ISD::FMA, MVT::f128, Expand);
294 setOperationAction(ISD::FMA, MVT::f16, Promote);
341 setOperationAction(ISD::FMA, MVT::v4f16, Expand);
372 setOperationAction(ISD::FMA, MVT::v8f16, Expand);
527 setOperationAction(ISD::FMA, MVT::v1f64, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 480 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
548 // NEON only has FMA instructions as of VFP4.
550 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
551 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
596 setOperationAction(ISD::FMA, MVT::f64, Expand);
[all...] |
