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    Searched refs:G5 (Results 1 - 3 of 3) sorted by null

  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.cpp 67 // G5 is not reserved in 64 bit mode.
69 Reserved.set(SP::G5);
  /external/llvm/lib/Target/Sparc/Disassembler/
SparcDisassembler.cpp 68 SP::G4, SP::G5, SP::G6, SP::G7,
  /external/llvm/lib/Target/Sparc/AsmParser/
SparcAsmParser.cpp 93 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,

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