| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILUtilityFunctions.h | 18 #define ExpandCaseTo32bitIntTypes(Instr) \
19 case Instr##_i32:
21 #define ExpandCaseTo32bitIntTruncTypes(Instr) \
22 case Instr##_i32i8: \
23 case Instr##_i32i16:
25 #define ExpandCaseToIntTypes(Instr) \
26 ExpandCaseTo32bitIntTypes(Instr)
28 #define ExpandCaseToIntTruncTypes(Instr) \
29 ExpandCaseTo32bitIntTruncTypes(Instr)
31 #define ExpandCaseToFloatTypes(Instr) \
[all...] |
| /art/compiler/utils/mips64/ |
| constants_mips64.h | 65 class Instr {
75 // to allocate or create instances of class Instr.
76 // Use the At(pc) function to create references to Instr.
77 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
80 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /external/llvm/lib/Target/ARM/ |
| ARMFeatures.h | 22 bool IsCPSRDead(InstrType *Instr);
25 inline bool isV8EligibleForIT(InstrType *Instr) {
26 switch (Instr->getOpcode()) {
53 return IsCPSRDead(Instr);
79 return Instr->getOperand(2).getReg() != ARM::PC;
84 return Instr->getOperand(0).getReg() != ARM::PC;
86 return Instr->getOperand(0).getReg() != ARM::PC &&
87 Instr->getOperand(2).getReg() != ARM::PC;
90 return Instr->getOperand(0).getReg() != ARM::PC &&
91 Instr->getOperand(1).getReg() != ARM::PC
[all...] |
| /art/compiler/utils/mips/ |
| constants_mips.h | 89 class Instr {
99 // to allocate or create instances of class Instr.
100 // Use the At(pc) function to create references to Instr.
101 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
104 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /art/compiler/utils/x86/ |
| constants_x86.h | 104 class Instr {
116 // to allocate or create instances of class Instr.
117 // Use the At(pc) function to create references to Instr.
118 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
121 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /art/compiler/utils/x86_64/ |
| constants_x86_64.h | 113 class Instr {
125 // to allocate or create instances of class Instr.
126 // Use the At(pc) function to create references to Instr.
127 static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); }
130 DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.h | 32 getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes,
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 85 Instruction *Instr = J;
86 Value *Dividend = Instr->getOperand(0);
87 Value *Divisor = Instr->getOperand(1);
142 PHINode *QuoPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2);
145 PHINode *RemPhi = SuccessorBuilder.CreatePHI(Instr->getType(), 2);
149 // Replace Instr with appropriate phi node
151 Instr->replaceAllUsesWith(QuoPhi);
153 Instr->replaceAllUsesWith(RemPhi);
154 Instr->eraseFromParent();
193 Instruction *Instr = J
[all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | 544 static const int kInstrSize = sizeof(Instr);
[all...] |
| constants-mips.h | 227 typedef int32_t Instr;
707 extern const Instr kPopInstruction;
709 extern const Instr kPushInstruction;
711 extern const Instr kPushRegPattern;
713 extern const Instr kPopRegPattern;
714 extern const Instr kLwRegFpOffsetPattern;
715 extern const Instr kSwRegFpOffsetPattern;
716 extern const Instr kLwRegFpNegOffsetPattern;
717 extern const Instr kSwRegFpNegOffsetPattern;
719 extern const Instr kRtMask
[all...] |
| assembler-mips.cc | 218 Instr* pc = reinterpret_cast<Instr*>(pc_);
219 Instr* instr = reinterpret_cast<Instr*>(instructions); local
221 *(pc + i) = *(instr + i);
275 const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
279 const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift)
283 const Instr kPushRegPattern = SW | (kRegister_sp_Code << kRsShift)
286 const Instr kPopRegPattern = LW | (kRegister_sp_Code << kRsShift
779 Instr instr = instr_at(l.pos()); local
805 Instr instr = instr_at(fixup_pos); local
873 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
886 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
899 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) local
912 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) local
925 Instr instr = opcode | fmt | (rt.code() << kRtShift) local
937 Instr instr = local
950 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
961 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); local
971 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) local
981 Instr instr = opcode | address; local
1373 Instr instr = BEQZC | (rs.code() << kRsShift) | offset; local
1388 Instr instr = BNEZC | (rs.code() << kRsShift) | offset; local
1639 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) local
1649 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
1816 Instr instr = SPECIAL | TGE | rs.code() << kRsShift local
1824 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift local
1832 Instr instr = local
1840 Instr instr = local
1849 Instr instr = local
1857 Instr instr = local
1951 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) local
2272 Instr instr = COP1 | fmt | ft.code() << kFtShift | local
2280 Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask); local
2287 Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask); local
2297 Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift local
2314 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); local
2321 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); local
2350 Instr instr = instr_at(pc); local
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600OptimizeVectorRegisters.cpp | 64 MachineInstr *Instr;
67 RegSeqInfo(MachineRegisterInfo &MRI, MachineInstr *MI) : Instr(MI) {
69 for (unsigned i = 1, e = Instr->getNumOperands(); i < e; i+=2) {
70 MachineOperand &MO = Instr->getOperand(i);
71 unsigned Chan = Instr->getOperand(i + 1).getImm();
81 return RSI.Instr == Instr;
181 unsigned Reg = RSI->Instr->getOperand(0).getReg();
182 MachineBasicBlock::iterator Pos = RSI->Instr;
186 unsigned SrcVec = BaseRSI->Instr->getOperand(0).getReg()
[all...] |
| /external/v8/src/arm64/ |
| instructions-arm64.h | 19 typedef uint32_t Instr;
99 V8_INLINE Instr InstructionBits() const {
100 return *reinterpret_cast<const Instr*>(this);
103 V8_INLINE void SetInstructionBits(Instr new_instr) {
104 *reinterpret_cast<Instr*>(this) = new_instr;
120 Instr Mask(uint32_t mask) const {
291 // The range of the branch instruction, expressed as 'instr +- range'.
410 const Instr kImmExceptionIsRedirectedCall = 0xca11;
414 const Instr kImmExceptionIsUnreachable = 0xdebf;
418 const Instr kImmExceptionIsPrintf = 0xdeb1
[all...] |
| assembler-arm64-inl.h | 577 Instruction* instr = reinterpret_cast<Instruction*>(pc);
578 DCHECK(instr->IsLdrLiteralX());
579 return reinterpret_cast<Address>(instr->ImmPCOffsetTarget());
603 Instruction* instr = reinterpret_cast<Instruction*>(candidate);
604 USE(instr);
605 DCHECK(instr->IsLdrLiteralX());
635 Instruction* instr = reinterpret_cast<Instruction*>(pc);
636 if (instr->IsMovz()) {
638 DCHECK(instr->following(1)->IsMovk());
639 DCHECK(instr->following(2)->IsMovk())
[all...] |
| assembler-arm64.h | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64PromoteConstant.cpp | 239 static bool shouldConvertUse(const Constant *Cst, const Instruction *Instr,
243 if (isa<const ShuffleVectorInst>(Instr) && OpIdx == 2)
247 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0)
251 if (isa<const InsertValueInst>(Instr) && OpIdx > 1)
254 if (isa<const AllocaInst>(Instr) && OpIdx > 0)
258 if (isa<const LoadInst>(Instr) && OpIdx > 0)
262 if (isa<const StoreInst>(Instr) && OpIdx > 1)
266 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0)
271 if (isa<const LandingPadInst>(Instr))
275 if (isa<const SwitchInst>(Instr))
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 528 // instructions instr is ignored.
532 int instructions_required(const Assembler* assembler, Instr instr = 0) const;
798 static const int kInstrSize = sizeof(Instr);
[all...] |
| assembler-arm.cc | 241 Instr* pc = reinterpret_cast<Instr*>(pc_);
242 Instr* instr = reinterpret_cast<Instr*>(instructions); local
244 *(pc + i) = *(instr + i);
404 const Instr kPushRegPattern =
408 const Instr kPopRegPattern =
411 const Instr kLdrPCImmedMask = 15 * B24 | 7 * B20 | 15 * B16;
412 const Instr kLdrPCImmedPattern = 5 * B24 | L | kRegister_pc_Code * B16
786 Instr instr = instr_at(pos); local
803 Instr instr = instr_at(pos); local
898 Instr instr = instr_at(l.pos()); local
1860 Instr instr; local
[all...] |
| constants-arm.h | 25 inline int DecodeConstantPoolLength(int instr) {
26 DCHECK((instr & kConstantPoolMarkerMask) == kConstantPoolMarker);
27 return ((instr >> 4) & 0xfff0) | (instr & 0xf);
55 // General constants are in an anonymous enum in class Instr.
120 // Instr is merely used by the Assembler to distinguish 32bit integers
124 typedef int32_t Instr;
413 // Note that the Assembler uses typedef int32_t Instr.
419 // Instruction* instr = Instruction::At(ptr);
420 // int type = instr->TypeValue()
[all...] |
| assembler-arm-inl.h | 304 Instr current_instr = Assembler::instr_at(pc_);
305 Instr next_instr = Assembler::instr_at(pc_ + Assembler::kInstrSize);
315 Instr current_instr = Assembler::instr_at(pc_);
416 void Assembler::emit(Instr x) {
418 *reinterpret_cast<Instr*>(pc_) = x;
458 Instr candidate_instr(Memory::int32_at(candidate));
557 Instr mov_instr = instr_at(pc);
558 Instr orr_instr_1 = instr_at(pc + kInstrSize);
559 Instr orr_instr_2 = instr_at(pc + 2 * kInstrSize);
560 Instr orr_instr_3 = instr_at(pc + 3 * kInstrSize)
579 Instr instr = Memory::int32_at(pc); local
[all...] |
| /external/v8/src/mips64/ |
| assembler-mips64.h | 534 static const int kInstrSize = sizeof(Instr);
[all...] |
| assembler-mips64.cc | 196 Instr* pc = reinterpret_cast<Instr*>(pc_);
197 Instr* instr = reinterpret_cast<Instr*>(instructions); local
199 *(pc + i) = *(instr + i);
253 const Instr kPopInstruction = DADDIU | (kRegister_sp_Code << kRsShift)
257 const Instr kPushInstruction = DADDIU | (kRegister_sp_Code << kRsShift)
261 const Instr kPushRegPattern = SD | (kRegister_sp_Code << kRsShift)
264 const Instr kPopRegPattern = LD | (kRegister_sp_Code << kRsShift
763 Instr instr = instr_at(l.pos()); local
789 Instr instr = instr_at(fixup_pos); local
857 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
870 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
883 Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) local
896 Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) local
909 Instr instr = opcode | fmt | (rt.code() << kRtShift) local
921 Instr instr = local
934 Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
945 Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); local
955 Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) local
965 Instr instr = opcode | address; local
1352 Instr instr = BEQZC | (rs.code() << kRsShift) | offset; local
1367 Instr instr = BNEZC | (rs.code() << kRsShift) | offset; local
1703 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) local
1713 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
1741 Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) local
1749 Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) local
2011 Instr instr = SPECIAL | TGE | rs.code() << kRsShift local
2019 Instr instr = SPECIAL | TGEU | rs.code() << kRsShift local
2027 Instr instr = local
2035 Instr instr = local
2044 Instr instr = local
2052 Instr instr = local
2122 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift | local
2142 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift | local
2162 Instr instr = COP1 | fmt << kRsShift | ft.code() << kFtShift | local
2197 Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) local
2498 Instr instr = COP1 | fmt | ft.code() << kFtShift | local
2506 Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask); local
2513 Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask); local
2524 Instr instr = COP1 | fmt | ft.code() << kFtShift | fs.code() << kFsShift local
2541 Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); local
2548 Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); local
2577 Instr instr = instr_at(pc); local
[all...] |
| constants-mips64.h | 189 typedef int32_t Instr;
721 extern const Instr kPopInstruction;
723 extern const Instr kPushInstruction;
725 extern const Instr kPushRegPattern;
727 extern const Instr kPopRegPattern;
728 extern const Instr kLwRegFpOffsetPattern;
729 extern const Instr kSwRegFpOffsetPattern;
730 extern const Instr kLwRegFpNegOffsetPattern;
731 extern const Instr kSwRegFpNegOffsetPattern;
733 extern const Instr kRtMask
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCDisassembler.h | 64 /// @param Instr - An MCInst to populate with the contents of the
77 virtual DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXImageOptimizer.cpp | 61 Instruction &Instr = *I;
69 Changed |= replaceIsTypePSampler(Instr);
72 Changed |= replaceIsTypePSurface(Instr);
75 Changed |= replaceIsTypePTexture(Instr);
|
