| /external/v8/src/mips/ |
| constants-mips.cc | 159 case JALR:
186 case JALR:
222 case JALR:
|
| assembler-mips-inl.h | 156 // that is the address of the instruction that follows J/JAL/JR/JALR
360 (instr2 & kFunctionFieldMask) == JALR)));
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| assembler-mips.cc | 540 ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
561 GetRdField(instr) == 0 && GetFunctionField(instr) == JALR;
568 GetRdField(instr) != 0 && GetFunctionField(instr) == JALR;
1432 void Assembler::jalr(Register rs, Register rd) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 381 JALR = ((1 << 3) + 1),
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| simulator-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.cc | 159 case JALR:
186 case JALR:
222 case JALR:
|
| assembler-mips64-inl.h | 148 // that is the address of the instruction that follows J/JAL/JR/JALR
351 Instr instr4 = Assembler::instr_at(pc_ + 4 * Assembler::kInstrSize); // jalr.
357 (instr4 & kFunctionFieldMask) == JALR);
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| constants-mips64.h | 358 JALR = ((1 << 3) + 1),
|
| assembler-mips64.cc | 518 ((function_field == JALR) || (rd_field == 0 && (function_field == JR))));
540 return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JALR;
1411 void Assembler::jalr(Register rs, Register rd) { function in class:v8::Assembler
[all...] |
| simulator-mips64.cc | [all...] |
| /external/valgrind/none/tests/mips32/ |
| branches.stdout.exp | 407 j, jalr, jr
408 J JALR JR :: 6, RSval: 0
409 J JALR JR :: 7, RSval: 1
410 J JALR JR :: 8, RSval: 2
411 J JALR JR :: 9, RSval: 3
412 J JALR JR :: 10, RSval: 4
413 J JALR JR :: 11, RSval: 5
414 J JALR JR :: 12, RSval: 6
415 J JALR JR :: 13, RSval: 7
416 J JALR JR :: 14, RSval:
[all...] |
| /external/valgrind/none/tests/mips64/ |
| branches.stdout.exp | 424 j, jalr, jr
425 J JALR JR :: 6, RSval: 0
426 J JALR JR :: 7, RSval: 1
427 J JALR JR :: 8, RSval: 2
428 J JALR JR :: 9, RSval: 3
429 J JALR JR :: 10, RSval: 4
430 J JALR JR :: 11, RSval: 5
431 J JALR JR :: 12, RSval: 6
432 J JALR JR :: 13, RSval: 7
433 J JALR JR :: 14, RSval:
[all...] |
| branch_and_jump_instructions.stdout.exp | [all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 51 if (MI.getOpcode() == Mips::JALR) {
52 // MIPS32r6/MIPS64r6 doesn't have a JR instruction and uses JALR instead.
53 // JALR is an indirect branch if the link register is $0.
81 case Mips::JALR:
82 // JALR is only a call if the link register is not $0. Otherwise it's an
|
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 317 case Mips::JALR:
318 // jalr $ra, $r1 => jalr $r1
319 return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
321 // jalr $ra, $r1 => jalr $r1
322 return isReg<Mips::RA_64>(MI, 0) && printAlias("jalr", MI, 1, OS);
|
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 98 // JALR, or JALR64 as appropriate for the target
109 // MIPS32r6 should use (JALR ZERO, $rs)
110 TmpInst0.setOpcode(Mips::JALR);
[all...] |
| MipsDelaySlotFiller.cpp | 551 case Mips::JALR:
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| MipsFastISel.cpp | [all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeMIPS_common.c | 142 #define JALR (HI(0) | LO(9))
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
