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    Searched refs:MCPhysReg (Results 1 - 25 of 72) sorted by null

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  /external/llvm/lib/CodeGen/
AllocationOrder.h 29 SmallVector<MCPhysReg, 16> Hints;
30 ArrayRef<MCPhysReg> Order;
43 ArrayRef<MCPhysReg> getOrder() const { return Order; }
RegisterClassInfo.cpp 51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
87 RCI.Order.reset(new MCPhysReg[NumRegs]);
90 SmallVector<MCPhysReg, 16> CSRAlias;
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
CallingConvLower.cpp 194 void CCState::getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs,
222 Regs.push_back(MCPhysReg(Locs[I].getLocReg()));
240 SmallVector<MCPhysReg, 8> RemainingRegs;
244 for (MCPhysReg PReg : RemainingRegs) {
  /external/llvm/lib/Target/R600/
AMDGPURegisterInfo.h 32 static const MCPhysReg CalleeSavedReg;
52 const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
AMDGPURegisterInfo.cpp 27 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
29 const MCPhysReg*
  /external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 33 std::unique_ptr<MCPhysReg[]> Order;
39 operator ArrayRef<MCPhysReg>() const {
56 const MCPhysReg *CalleeSaved;
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
CallingConvLower.h 165 ForwardedRegister(unsigned VReg, MCPhysReg PReg, MVT VT)
168 MCPhysReg PReg;
318 unsigned getFirstUnallocated(ArrayRef<MCPhysReg> Regs) const {
345 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs) {
386 unsigned AllocateReg(ArrayRef<MCPhysReg> Regs, const MCPhysReg *ShadowRegs) {
418 ArrayRef<MCPhysReg> ShadowRegs) {
487 void getRemainingRegParmsForType(SmallVectorImpl<MCPhysReg> &Regs, MVT VT,
  /external/llvm/lib/Target/BPF/
BPFRegisterInfo.h 28 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.h 29 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
MSP430RegisterInfo.cpp 38 const MCPhysReg*
42 static const MCPhysReg CalleeSavedRegs[] = {
47 static const MCPhysReg CalleeSavedRegsFP[] = {
52 static const MCPhysReg CalleeSavedRegsIntr[] = {
58 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
  /external/llvm/lib/Target/X86/
X86MachineFunctionInfo.cpp 23 for (const MCPhysReg *CSR =
X86RegisterInfo.h 93 const MCPhysReg *
  /external/llvm/lib/Target/Hexagon/
HexagonRegisterInfo.h 44 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsABIInfo.cpp 19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
21 static const MCPhysReg Mips64IntRegs[8] = {
26 const ArrayRef<MCPhysReg> MipsABIInfo::GetByValArgRegs() const {
34 const ArrayRef<MCPhysReg> MipsABIInfo::GetVarArgRegs() const {
MipsABIInfo.h 49 const ArrayRef<MCPhysReg> GetByValArgRegs() const;
52 const ArrayRef<MCPhysReg> GetVarArgRegs() const;
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.h 27 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.h 32 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/include/llvm/MC/
MCRegisterInfo.h 27 typedef uint16_t MCPhysReg;
32 typedef const MCPhysReg* iterator;
33 typedef const MCPhysReg* const_iterator;
162 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
163 const MCPhysReg *DiffLists; // Pointer to the difflists array
193 const MCPhysReg *List;
202 void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
212 MCPhysReg D = *List++;
247 const MCPhysReg (*RURoots)[2]
    [all...]
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.cpp 80 const MCPhysReg *
82 static const MCPhysReg CalleeSavedRegs[] = { 0 };
NVPTXRegisterInfo.h 38 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/lib/Target/ARM/
ARMBaseRegisterInfo.h 72 const MCPhysReg *CSRegs) {
94 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
126 ArrayRef<MCPhysReg> Order,
127 SmallVectorImpl<MCPhysReg> &Hints,
ARMCallingConv.h 31 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
74 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
75 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
76 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
77 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
126 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
127 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.h 46 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/lib/Target/Mips/
MipsRegisterInfo.h 44 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 38 typedef const MCPhysReg* iterator;
39 typedef const MCPhysReg* const_iterator;
55 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
196 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
432 virtual const MCPhysReg*
692 ArrayRef<MCPhysReg> Order,
693 SmallVectorImpl<MCPhysReg> &Hints,
    [all...]

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