| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUCodeEmitter.h | 21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
22 virtual uint64_t getMachineOpValue(const MachineInstr &MI,
24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI,
28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI,
32 virtual uint64_t VOPPostEncode(const MachineInstr &MI,
36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI,
40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo)
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| AMDGPUMCInstLower.h | 1 //===- AMDGPUMCInstLower.h MachineInstr Lowering Interface ------*- C++ -*-===//
16 class MachineInstr;
23 /// lower - Lower a MachineInstr to an MCInst
24 void lower(const MachineInstr *MI, MCInst &OutMI) const;
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| AMDGPUInstrInfo.h | 37 class MachineInstr;
51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
55 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
57 bool hasLoadFromStackSlot(const MachineInstr *MI,
60 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
61 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
63 bool hasStoreFromStackSlot(const MachineInstr *MI,
67 MachineInstr *
90 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF
[all...] |
| R600InstrInfo.h | 29 class MachineInstr;
48 bool isTrig(const MachineInstr &MI) const;
55 bool isVector(const MachineInstr &MI) const;
57 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
75 bool isPredicated(const MachineInstr *MI) const;
77 bool isPredicable(MachineInstr *MI) const;
94 bool DefinesPredicate(MachineInstr *MI,
103 bool PredicateInstruction(MachineInstr *MI,
107 const MachineInstr *MI,
115 bool hasFlagOperand(const MachineInstr &MI) const
[all...] |
| AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI,
66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI,
71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI,
78 MachineInstr *
140 MachineInstr *
142 MachineInstr *MI
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 50 unsigned isLoadFromStackSlot(const MachineInstr *MI,
58 unsigned isStoreToStackSlot(const MachineInstr *MI,
74 bool analyzeCompare(const MachineInstr *MI,
92 SmallVectorImpl<MachineInstr*> &NewMIs) const;
103 SmallVectorImpl<MachineInstr*> &NewMIs) const;
113 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
117 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
119 MachineInstr *LoadMI) const override
[all...] |
| HexagonMachineFunctionInfo.h | 30 std::vector<MachineInstr*> AllocaAdjustInsts;
34 std::map<const MachineInstr*, unsigned> PacketInfo;
48 void addAllocaAdjustInst(MachineInstr* MI) {
51 const std::vector<MachineInstr*>& getAllocaAdjustInsts() {
58 void setStartPacket(MachineInstr* MI) {
61 void setEndPacket(MachineInstr* MI) {
64 bool isStartPacket(const MachineInstr* MI) const {
68 bool isEndPacket(const MachineInstr* MI) const {
|
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 73 bool isTriviallyReMaterializable(const MachineInstr *MI,
88 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
99 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
116 virtual int getSPAdjust(const MachineInstr *MI) const;
124 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
135 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
143 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
155 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
164 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
172 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 38 #include "llvm/CodeGen/MachineInstr.h"
89 std::vector<MachineInstr*> Kills;
94 bool removeKill(MachineInstr *MI) {
95 std::vector<MachineInstr*>::iterator
104 MachineInstr *findKill(const MachineBasicBlock *MBB) const;
137 std::vector<MachineInstr *> PhysRegDef;
142 std::vector<MachineInstr *> PhysRegUse;
148 DenseMap<MachineInstr*, unsigned> DistanceMap;
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI)
[all...] |
| DFAPacketizer.h | 36 class MachineInstr;
76 bool canReserveResources(llvm::MachineInstr *MI);
80 void reserveResources(llvm::MachineInstr *MI);
101 std::vector<MachineInstr*> CurrentPacketMIs;
106 std::map<MachineInstr*, SUnit*> MIToSUnit;
122 virtual MachineBasicBlock::iterator addToPacket(MachineInstr *MI) {
130 void endPacket(MachineBasicBlock *MBB, MachineInstr *MI);
138 virtual bool ignorePseudoInstruction(MachineInstr *I,
145 virtual bool isSoloInstruction(MachineInstr *MI) {
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| MachineInstrBundle.h | 46 inline MachineInstr *getBundleStart(MachineInstr *MI) {
53 inline const MachineInstr *getBundleStart(const MachineInstr *MI) {
62 getBundleEnd(MachineInstr *MI) {
71 getBundleEnd(const MachineInstr *MI) {
83 /// MachineInstr, or all operands on a bundle of MachineInstrs. This class is
96 MachineInstr::mop_iterator OpI, OpE;
117 explicit MachineOperandIteratorBase(MachineInstr *MI, bool WholeBundle) {
199 SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops = nullptr)
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.h | 38 * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
40 * virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
55 virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
57 bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
58 bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
59 bool isReadSpecialReg(MachineInstr &MI) const;
61 virtual bool CanTailMerge(const MachineInstr *MI) const;
70 unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
|
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 32 typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
50 virtual void Observe(MachineInstr *MI, unsigned Count,
58 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.h | 20 class MachineInstr;
33 void EmitInstruction(const MachineInstr *MI) override;
35 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
38 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
134 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
181 int getSPAdjust(const MachineInstr *MI) const override;
189 bool isCoalescableExtInstr(const MachineInstr &MI,
193 unsigned isLoadFromStackSlot(const MachineInstr *MI,
198 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
201 unsigned isStoreToStackSlot(const MachineInstr *MI,
206 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
209 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
213 const MachineInstr *Orig
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUInstrInfo.h | 37 class MachineInstr;
51 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
54 unsigned isLoadFromStackSlot(const MachineInstr *MI,
56 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
58 bool hasLoadFromStackSlot(const MachineInstr *MI,
61 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
62 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
64 bool hasStoreFromStackSlot(const MachineInstr *MI,
68 MachineInstr *
88 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI
[all...] |
| SIInstrInfo.h | 42 unsigned split64BitImm(SmallVectorImpl<MachineInstr *> &Worklist,
50 void splitScalar64BitUnaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
51 MachineInstr *Inst, unsigned Opcode) const;
53 void splitScalar64BitBinaryOp(SmallVectorImpl<MachineInstr *> &Worklist,
54 MachineInstr *Inst, unsigned Opcode) const;
56 void splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist,
57 MachineInstr *Inst) const;
58 void splitScalar64BitBFE(SmallVectorImpl<MachineInstr *> &Worklist,
59 MachineInstr *Inst) const;
61 void addDescImplicitUseDef(const MCInstrDesc &Desc, MachineInstr *MI) const
[all...] |
| AMDGPUMCInstLower.h | 1 //===- AMDGPUMCInstLower.h MachineInstr Lowering Interface ------*- C++ -*-===//
17 class MachineInstr;
28 /// \brief Lower a MachineInstr to an MCInst
29 void lower(const MachineInstr *MI, MCInst &OutMI) const;
|
| R600InstrInfo.h | 29 class MachineInstr;
37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
71 bool isTrig(const MachineInstr &MI) const;
85 bool canBeConsideredALU(const MachineInstr *MI) const;
88 bool isTransOnly(const MachineInstr *MI) const;
90 bool isVectorOnly(const MachineInstr *MI) const;
94 bool usesVertexCache(const MachineInstr *MI) const;
96 bool usesTextureCache(const MachineInstr *MI) const;
99 bool usesAddressRegister(MachineInstr *MI) const;
100 bool definesAddressRegister(MachineInstr *MI) const
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 48 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
50 bool isAsCheapAsAMove(const MachineInstr *MI) const override;
52 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
56 areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
59 unsigned isLoadFromStackSlot(const MachineInstr *MI,
61 unsigned isStoreToStackSlot(const MachineInstr *MI,
66 bool hasShiftedReg(const MachineInstr *MI) const;
70 bool hasExtendedReg(const MachineInstr *MI) const;
73 bool isGPRZero(const MachineInstr *MI) const
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterHandler.h | 23 class MachineInstr;
54 virtual void beginInstruction(const MachineInstr *MI) = 0;
|
| DbgValueHistoryCalculator.h | 19 class MachineInstr;
33 typedef std::pair<const MachineInstr *, const MachineInstr *> InstrRange;
43 void startInstrRange(InlinedVariable Var, const MachineInstr &MI);
44 void endInstrRange(InlinedVariable Var, const MachineInstr &MI);
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.h | 30 EmitInstrWithCustomInserter(MachineInstr *MI,
53 MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr *MI,
57 MachineInstr *MI,
61 MachineInstr *MI,
65 MachineInstr *MI,
70 MachineInstr *MI, MachineBasicBlock *BB) const;
74 MachineInstr *MI, MachineBasicBlock *BB) const;
78 MachineInstr *MI, MachineBasicBlock *BB )const;
|
| MipsMCInstLower.h | 1 //===-- MipsMCInstLower.h - Lower MachineInstr to MCInst -------*- C++ -*--===//
21 class MachineInstr;
25 /// MipsMCInstLower - This class is used to lower an MachineInstr into an
34 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
42 void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
43 void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
46 bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 56 const MachineInstr &MI, unsigned DefIdx,
69 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
85 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
97 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
127 bool isPredicated(const MachineInstr *MI) const override;
129 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
135 bool PredicateInstruction(MachineInstr *MI,
141 bool DefinesPredicate(MachineInstr *MI,
144 bool isPredicable(MachineInstr *MI) const override;
146 /// GetInstSize - Returns the size of the specified MachineInstr
[all...] |
