1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 16 17 #include "HexagonRegisterInfo.h" 18 #include "MCTargetDesc/HexagonBaseInfo.h" 19 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 20 #include "llvm/Target/TargetFrameLowering.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "HexagonGenInstrInfo.inc" 25 26 namespace llvm { 27 28 struct EVT; 29 class HexagonSubtarget; 30 class HexagonInstrInfo : public HexagonGenInstrInfo { 31 virtual void anchor(); 32 const HexagonRegisterInfo RI; 33 const HexagonSubtarget &Subtarget; 34 typedef unsigned Opcode_t; 35 36 public: 37 explicit HexagonInstrInfo(HexagonSubtarget &ST); 38 39 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 40 /// such, whenever a client has an instance of instruction info, it should 41 /// always be able to get register info as well (through this method). 42 /// 43 const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 44 45 /// isLoadFromStackSlot - If the specified machine instruction is a direct 46 /// load from a stack slot, return the virtual or physical register number of 47 /// the destination along with the FrameIndex of the loaded stack slot. If 48 /// not, return 0. This predicate must return 0 if the instruction has 49 /// any side effects other than loading from the stack slot. 50 unsigned isLoadFromStackSlot(const MachineInstr *MI, 51 int &FrameIndex) const override; 52 53 /// isStoreToStackSlot - If the specified machine instruction is a direct 54 /// store to a stack slot, return the virtual or physical register number of 55 /// the source reg along with the FrameIndex of the loaded stack slot. If 56 /// not, return 0. This predicate must return 0 if the instruction has 57 /// any side effects other than storing to the stack slot. 58 unsigned isStoreToStackSlot(const MachineInstr *MI, 59 int &FrameIndex) const override; 60 61 62 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 63 MachineBasicBlock *&FBB, 64 SmallVectorImpl<MachineOperand> &Cond, 65 bool AllowModify) const override; 66 67 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 68 69 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 70 MachineBasicBlock *FBB, 71 const SmallVectorImpl<MachineOperand> &Cond, 72 DebugLoc DL) const override; 73 74 bool analyzeCompare(const MachineInstr *MI, 75 unsigned &SrcReg, unsigned &SrcReg2, 76 int &Mask, int &Value) const override; 77 78 void copyPhysReg(MachineBasicBlock &MBB, 79 MachineBasicBlock::iterator I, DebugLoc DL, 80 unsigned DestReg, unsigned SrcReg, 81 bool KillSrc) const override; 82 83 void storeRegToStackSlot(MachineBasicBlock &MBB, 84 MachineBasicBlock::iterator MBBI, 85 unsigned SrcReg, bool isKill, int FrameIndex, 86 const TargetRegisterClass *RC, 87 const TargetRegisterInfo *TRI) const override; 88 89 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, 90 SmallVectorImpl<MachineOperand> &Addr, 91 const TargetRegisterClass *RC, 92 SmallVectorImpl<MachineInstr*> &NewMIs) const; 93 94 void loadRegFromStackSlot(MachineBasicBlock &MBB, 95 MachineBasicBlock::iterator MBBI, 96 unsigned DestReg, int FrameIndex, 97 const TargetRegisterClass *RC, 98 const TargetRegisterInfo *TRI) const override; 99 100 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 101 SmallVectorImpl<MachineOperand> &Addr, 102 const TargetRegisterClass *RC, 103 SmallVectorImpl<MachineInstr*> &NewMIs) const; 104 105 /// expandPostRAPseudo - This function is called for all pseudo instructions 106 /// that remain after register allocation. Many pseudo instructions are 107 /// created to help register allocation. This is the place to convert them 108 /// into real instructions. The target can edit MI in place, or it can insert 109 /// new instructions and erase MI. The function should return true if 110 /// anything was changed. 111 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 112 113 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 114 ArrayRef<unsigned> Ops, 115 int FrameIndex) const override; 116 117 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, 118 ArrayRef<unsigned> Ops, 119 MachineInstr *LoadMI) const override { 120 return nullptr; 121 } 122 123 unsigned createVR(MachineFunction* MF, MVT VT) const; 124 125 bool isBranch(const MachineInstr *MI) const; 126 bool isPredicable(MachineInstr *MI) const override; 127 bool PredicateInstruction(MachineInstr *MI, 128 const SmallVectorImpl<MachineOperand> &Cond) const override; 129 130 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 131 unsigned ExtraPredCycles, 132 const BranchProbability &Probability) const override; 133 134 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 135 unsigned NumTCycles, unsigned ExtraTCycles, 136 MachineBasicBlock &FMBB, 137 unsigned NumFCycles, unsigned ExtraFCycles, 138 const BranchProbability &Probability) const override; 139 140 bool isPredicated(const MachineInstr *MI) const override; 141 bool isPredicated(unsigned Opcode) const; 142 bool isPredicatedTrue(const MachineInstr *MI) const; 143 bool isPredicatedTrue(unsigned Opcode) const; 144 bool isPredicatedNew(const MachineInstr *MI) const; 145 bool isPredicatedNew(unsigned Opcode) const; 146 bool DefinesPredicate(MachineInstr *MI, 147 std::vector<MachineOperand> &Pred) const override; 148 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 149 const SmallVectorImpl<MachineOperand> &Pred2) const override; 150 151 bool 152 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 153 154 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 155 const BranchProbability &Probability) const override; 156 157 DFAPacketizer * 158 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override; 159 160 bool isSchedulingBoundary(const MachineInstr *MI, 161 const MachineBasicBlock *MBB, 162 const MachineFunction &MF) const override; 163 bool isValidOffset(const int Opcode, const int Offset) const; 164 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 165 bool isMemOp(const MachineInstr *MI) const; 166 bool isSpillPredRegOp(const MachineInstr *MI) const; 167 bool isU6_3Immediate(const int value) const; 168 bool isU6_2Immediate(const int value) const; 169 bool isU6_1Immediate(const int value) const; 170 bool isU6_0Immediate(const int value) const; 171 bool isS4_3Immediate(const int value) const; 172 bool isS4_2Immediate(const int value) const; 173 bool isS4_1Immediate(const int value) const; 174 bool isS4_0Immediate(const int value) const; 175 bool isS12_Immediate(const int value) const; 176 bool isU6_Immediate(const int value) const; 177 bool isS8_Immediate(const int value) const; 178 bool isS6_Immediate(const int value) const; 179 180 bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const; 181 bool isConditionalTransfer(const MachineInstr* MI) const; 182 bool isConditionalALU32 (const MachineInstr* MI) const; 183 bool isConditionalLoad (const MachineInstr* MI) const; 184 bool isConditionalStore(const MachineInstr* MI) const; 185 bool isNewValueInst(const MachineInstr* MI) const; 186 bool isNewValue(const MachineInstr* MI) const; 187 bool isDotNewInst(const MachineInstr* MI) const; 188 int GetDotOldOp(const int opc) const; 189 int GetDotNewOp(const MachineInstr* MI) const; 190 int GetDotNewPredOp(MachineInstr *MI, 191 const MachineBranchProbabilityInfo 192 *MBPI) const; 193 bool mayBeNewStore(const MachineInstr* MI) const; 194 bool isDeallocRet(const MachineInstr *MI) const; 195 unsigned getInvertedPredicatedOpcode(const int Opc) const; 196 bool isExtendable(const MachineInstr* MI) const; 197 bool isExtended(const MachineInstr* MI) const; 198 bool isPostIncrement(const MachineInstr* MI) const; 199 bool isNewValueStore(const MachineInstr* MI) const; 200 bool isNewValueStore(unsigned Opcode) const; 201 bool isNewValueJump(const MachineInstr* MI) const; 202 bool isNewValueJumpCandidate(const MachineInstr *MI) const; 203 204 205 void immediateExtend(MachineInstr *MI) const; 206 bool isConstExtended(MachineInstr *MI) const; 207 int getDotNewPredJumpOp(MachineInstr *MI, 208 const MachineBranchProbabilityInfo *MBPI) const; 209 unsigned getAddrMode(const MachineInstr* MI) const; 210 bool isOperandExtended(const MachineInstr *MI, 211 unsigned short OperandNum) const; 212 unsigned short getCExtOpNum(const MachineInstr *MI) const; 213 int getMinValue(const MachineInstr *MI) const; 214 int getMaxValue(const MachineInstr *MI) const; 215 bool NonExtEquivalentExists (const MachineInstr *MI) const; 216 short getNonExtOpcode(const MachineInstr *MI) const; 217 bool PredOpcodeHasJMP_c(Opcode_t Opcode) const; 218 bool PredOpcodeHasNot(Opcode_t Opcode) const; 219 int getCondOpcode(int Opc, bool sense) const; 220 221 }; 222 223 } 224 225 #endif 226
