| /art/compiler/dex/quick/arm/ |
| backend_arm.h | 23 class Mir2Lir;
27 Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
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| target_arm.cc | 577 : Mir2Lir(cu, mir_graph, arena),
591 Mir2Lir* ArmCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
931 Mir2Lir::InstallLiteralPools();
[all...] |
| /art/compiler/dex/quick/arm64/ |
| backend_arm64.h | 23 class Mir2Lir;
27 Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
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| target_arm64.cc | 607 : Mir2Lir(cu, mir_graph, arena),
619 Mir2Lir* Arm64CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
874 Mir2Lir::InstallLiteralPools();
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| /art/compiler/dex/quick/mips/ |
| backend_mips.h | 23 class Mir2Lir;
27 Mir2Lir* MipsCodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
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| codegen_mips.h | 28 class MipsMir2Lir FINAL : public Mir2Lir {
32 explicit InToRegStorageMipsMapper(Mir2Lir* m2l) : m2l_(m2l), cur_core_reg_(0) {}
38 Mir2Lir* m2l_;
45 explicit InToRegStorageMips64Mapper(Mir2Lir* m2l) : m2l_(m2l), cur_arg_reg_(0) {}
51 Mir2Lir* m2l_;
97 /// @copydoc Mir2Lir::UnconditionallyMarkGCCard(RegStorage)
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| call_mips.cc | 318 StackOverflowSlowPath(Mir2Lir* m2l, LIR* branch, size_t sp_displace)
421 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
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| int_mips.cc | 596 Mir2Lir::GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2, flags);
831 Mir2Lir::GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
904 Mir2Lir::GenIntToLong(rl_dest, rl_src);
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| /art/compiler/dex/quick/x86/ |
| backend_x86.h | 23 class Mir2Lir;
27 Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
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| codegen_x86.h | 31 class X86Mir2Lir FINAL : public Mir2Lir {
35 explicit InToRegStorageX86_64Mapper(Mir2Lir* m2l)
43 Mir2Lir* m2l_;
50 explicit InToRegStorageX86Mapper(Mir2Lir* m2l)
104 /// @copydoc Mir2Lir::UnconditionallyMarkGCCard(RegStorage)
[all...] |
| utility_x86.cc | [all...] |
| call_x86.cc | 196 StackOverflowSlowPath(Mir2Lir* m2l, LIR* branch, size_t sp_displace)
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| /art/compiler/dex/quick/ |
| mir_to_lir-inl.h | 29 inline void Mir2Lir::ClobberBody(RegisterInfo* p) {
46 inline LIR* Mir2Lir::RawLIR(DexOffset dalvik_offset, int opcode, int op0,
71 inline LIR* Mir2Lir::NewLIR0(int opcode) {
81 inline LIR* Mir2Lir::NewLIR1(int opcode, int dest) {
91 inline LIR* Mir2Lir::NewLIR2(int opcode, int dest, int src1) {
101 inline LIR* Mir2Lir::NewLIR2NoDest(int opcode, int src, int info) {
111 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) {
121 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) {
131 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1,
145 inline void Mir2Lir::SetupRegMask(ResourceMask* mask, int reg)
[all...] |
| ralloc_util.cc | 35 void Mir2Lir::ResetRegPool() {
45 Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask)
62 Mir2Lir::RegisterPool::RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena,
143 void Mir2Lir::DumpRegPool(ArenaVector<RegisterInfo*>* regs) {
155 void Mir2Lir::DumpCoreRegPool() {
160 void Mir2Lir::DumpFpRegPool() {
165 void Mir2Lir::DumpRegPools() {
172 void Mir2Lir::Clobber(RegStorage reg) {
198 void Mir2Lir::ClobberAliases(RegisterInfo* info, uint32_t clobber_mask)
[all...] |
| gen_loadstore.cc | 31 LIR* Mir2Lir::LoadConstant(RegStorage r_dest, int value) {
44 void Mir2Lir::LoadValueDirect(RegLocation rl_src, RegStorage r_dest) {
73 void Mir2Lir::LoadValueDirectFixed(RegLocation rl_src, RegStorage r_dest) {
84 void Mir2Lir::LoadValueDirectWide(RegLocation rl_src, RegStorage r_dest) {
103 void Mir2Lir::LoadValueDirectWideFixed(RegLocation rl_src, RegStorage r_dest) {
109 RegLocation Mir2Lir::LoadValue(RegLocation rl_src, RegisterClass op_kind) {
135 void Mir2Lir::StoreValue(RegLocation rl_dest, RegLocation rl_src) {
193 RegLocation Mir2Lir::LoadValueWide(RegLocation rl_src, RegisterClass op_kind) {
220 void Mir2Lir::StoreValueWide(RegLocation rl_dest, RegLocation rl_src) {
278 void Mir2Lir::StoreFinalValue(RegLocation rl_dest, RegLocation rl_src)
[all...] |
| codegen_util.cc | 61 bool Mir2Lir::IsInexpensiveConstant(RegLocation rl_src) {
88 void Mir2Lir::MarkSafepointPC(LIR* inst) {
97 void Mir2Lir::MarkSafepointPCAfter(LIR* after) {
114 void Mir2Lir::UnlinkLIR(LIR* lir) {
134 void Mir2Lir::NopLIR(LIR* lir) {
141 void Mir2Lir::SetMemRefType(LIR* lir, bool is_load, int mem_type) {
181 void Mir2Lir::AnnotateDalvikRegAccess(LIR* lir, int reg_id, bool is_load,
199 void Mir2Lir::DumpLIRInsn(LIR* lir, unsigned char* base_addr) {
292 void Mir2Lir::DumpPromotionMap() {
319 void Mir2Lir::UpdateLIROffsets()
[all...] |
| quick_compiler.h | 26 class Mir2Lir;
55 static Mir2Lir* GetCodeGenerator(CompilationUnit* cu, void* compilation_unit);
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| gen_common.cc | 61 void Mir2Lir::GenIfNullUseHelperImm(RegStorage r_result, QuickEntrypointEnum trampoline, int imm) {
64 CallHelperImmMethodSlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont,
91 RegStorage Mir2Lir::GenGetOtherTypeForSgetSput(const MirSFieldLoweringInfo& field_info,
129 class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath {
134 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, int storage_index,
174 void Mir2Lir::GenBarrier() {
181 void Mir2Lir::GenDivZeroException() {
186 void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) {
191 void Mir2Lir::GenDivZeroCheck(RegStorage reg) {
196 void Mir2Lir::AddDivZeroCheckSlowPath(LIR* branch)
[all...] |
| gen_invoke.cc | 48 void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) {
49 class IntrinsicSlowPathPath : public Mir2Lir::LIRSlowPath {
51 IntrinsicSlowPathPath(Mir2Lir* m2l, CallInfo* info_in, LIR* branch_in, LIR* resume_in)
81 RegStorage Mir2Lir::CallHelperSetup(QuickEntrypointEnum trampoline) {
89 LIR* Mir2Lir::CallHelper(RegStorage r_tgt, QuickEntrypointEnum trampoline, bool safepoint_pc,
103 void Mir2Lir::CallRuntimeHelper(QuickEntrypointEnum trampoline, bool safepoint_pc) {
109 void Mir2Lir::CallRuntimeHelperImm(QuickEntrypointEnum trampoline, int arg0, bool safepoint_pc) {
116 void Mir2Lir::CallRuntimeHelperReg(QuickEntrypointEnum trampoline, RegStorage arg0,
124 void Mir2Lir::CallRuntimeHelperRegLocation(QuickEntrypointEnum trampoline, RegLocation arg0,
136 void Mir2Lir::CallRuntimeHelperImmImm(QuickEntrypointEnum trampoline, int arg0, int arg1
[all...] |
| mir_to_lir.cc | 27 class Mir2Lir::SpecialSuspendCheckSlowPath : public Mir2Lir::LIRSlowPath {
29 SpecialSuspendCheckSlowPath(Mir2Lir* m2l, LIR* branch, LIR* cont)
90 RegisterClass Mir2Lir::ShortyToRegClass(char shorty_type) {
107 void Mir2Lir::LockArg(size_t in_position) {
115 RegStorage Mir2Lir::LoadArg(size_t in_position, RegisterClass reg_class, bool wide) {
165 void Mir2Lir::LoadArgDirect(size_t in_position, RegLocation rl_dest) {
207 void Mir2Lir::SpillArg(size_t in_position) {
219 void Mir2Lir::UnspillArg(size_t in_position) {
231 Mir2Lir::SpecialSuspendCheckSlowPath* Mir2Lir::GenSpecialSuspendTest()
[all...] |
| local_optimizations.cc | 71 void Mir2Lir::ConvertMemOpIntoMove(LIR* orig_lir, RegStorage dest, RegStorage src) {
85 void Mir2Lir::DumpDependentInsnPair(LIR* check_lir, LIR* this_lir, const char* type) {
93 inline void Mir2Lir::EliminateLoad(LIR* lir, int reg_id) {
148 void Mir2Lir::ApplyLoadStoreElimination(LIR* head_lir, LIR* tail_lir) {
319 void Mir2Lir::ApplyLoadHoisting(LIR* head_lir, LIR* tail_lir) {
509 void Mir2Lir::ApplyLocalOptimizations(LIR* head_lir, LIR* tail_lir) {
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| dex_file_method_inliner.h | 38 class Mir2Lir;
80 bool GenIntrinsic(Mir2Lir* backend, CallInfo* info) LOCKS_EXCLUDED(lock_);
90 bool GenSpecial(Mir2Lir* backend, uint32_t method_idx) LOCKS_EXCLUDED(lock_);
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| quick_cfi_test.cc | 88 std::unique_ptr<Mir2Lir> m2l(QuickCompiler::GetCodeGenerator(&cu, nullptr));
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| mir_to_lir.h | 209 class Mir2Lir {
422 RegisterPool(Mir2Lir* m2l, ArenaAllocator* arena,
451 Mir2Lir* const m2l_;
499 LIRSlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont = nullptr)
518 Mir2Lir* const m2l_;
532 ScopedMemRefType(Mir2Lir* m2l, ResourceMask::ResourceBit new_mem_ref_type)
543 Mir2Lir* const m2l_;
549 virtual ~Mir2Lir() {}
[all...] |
| /art/compiler/dex/ |
| compiler_ir.h | 36 class Mir2Lir;
194 std::unique_ptr<Mir2Lir> cg; // Target-specific codegen.
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