/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorTypes.cpp | 160 EVT NewVT = N->getValueType(0).getVectorElementType(); 162 NewVT, N->getOperand(0)); 176 EVT NewVT = N->getValueType(0).getVectorElementType(); 178 return DAG.getConvertRndSat(NewVT, SDLoc(N), 179 Op0, DAG.getValueType(NewVT), 193 EVT NewVT = N->getValueType(0).getVectorElementType(); 196 NewVT, Op, N->getOperand(1)); [all...] |
LegalizeTypesGeneric.cpp | 218 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); 231 NewVT, 2*OldElts), 238 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 242 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); 378 EVT NewVT = TLI.getTypeToTransformTo(*DAG.getContext(), OldVT); 400 NewVT, NewElts.size()),
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LegalizeVectorOps.cpp | 456 EVT NewVT; 459 NewVT = VT.widenIntegerVectorElementType(*DAG.getContext()); 460 assert(NewVT.isSimple() && "Promoting to a non-simple vector type!"); 461 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) { 465 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) { 472 SDValue promoted = DAG.getNode(NewOpc, SDLoc(Op), NewVT, Op.getOperand(0)); [all...] |
DAGCombiner.cpp | [all...] |
SelectionDAG.cpp | [all...] |
LegalizeDAG.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.h | 803 EVT NewVT) const override; [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineCalls.cpp | [all...] |
/external/llvm/include/llvm/Target/ |
TargetLowering.h | [all...] |
/external/llvm/lib/Target/R600/ |
R600ISelLowering.cpp | [all...] |
AMDGPUISelLowering.cpp | 452 EVT NewVT) const { 454 unsigned NewSize = NewVT.getStoreSizeInBits(); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |