1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is emits an assembly printer for the current target. 11 // Note that this is currently fairly skeletal, but will grow over time. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "AsmWriterInst.h" 16 #include "CodeGenTarget.h" 17 #include "SequenceToOffsetTable.h" 18 #include "llvm/ADT/SmallString.h" 19 #include "llvm/ADT/StringExtras.h" 20 #include "llvm/ADT/Twine.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/Format.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/TableGen/Error.h" 25 #include "llvm/TableGen/Record.h" 26 #include "llvm/TableGen/TableGenBackend.h" 27 #include <algorithm> 28 #include <cassert> 29 #include <map> 30 #include <vector> 31 using namespace llvm; 32 33 #define DEBUG_TYPE "asm-writer-emitter" 34 35 namespace { 36 class AsmWriterEmitter { 37 RecordKeeper &Records; 38 CodeGenTarget Target; 39 std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap; 40 const std::vector<const CodeGenInstruction*> *NumberedInstructions; 41 std::vector<AsmWriterInst> Instructions; 42 std::vector<std::string> PrintMethods; 43 public: 44 AsmWriterEmitter(RecordKeeper &R); 45 46 void run(raw_ostream &o); 47 48 private: 49 void EmitPrintInstruction(raw_ostream &o); 50 void EmitGetRegisterName(raw_ostream &o); 51 void EmitPrintAliasInstruction(raw_ostream &O); 52 53 AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { 54 assert(ID < NumberedInstructions->size()); 55 std::map<const CodeGenInstruction*, AsmWriterInst*>::const_iterator I = 56 CGIAWIMap.find(NumberedInstructions->at(ID)); 57 assert(I != CGIAWIMap.end() && "Didn't find inst!"); 58 return I->second; 59 } 60 void FindUniqueOperandCommands(std::vector<std::string> &UOC, 61 std::vector<unsigned> &InstIdxs, 62 std::vector<unsigned> &InstOpsUsed) const; 63 }; 64 } // end anonymous namespace 65 66 static void PrintCases(std::vector<std::pair<std::string, 67 AsmWriterOperand> > &OpsToPrint, raw_ostream &O) { 68 O << " case " << OpsToPrint.back().first << ": "; 69 AsmWriterOperand TheOp = OpsToPrint.back().second; 70 OpsToPrint.pop_back(); 71 72 // Check to see if any other operands are identical in this list, and if so, 73 // emit a case label for them. 74 for (unsigned i = OpsToPrint.size(); i != 0; --i) 75 if (OpsToPrint[i-1].second == TheOp) { 76 O << "\n case " << OpsToPrint[i-1].first << ": "; 77 OpsToPrint.erase(OpsToPrint.begin()+i-1); 78 } 79 80 // Finally, emit the code. 81 O << TheOp.getCode(); 82 O << "break;\n"; 83 } 84 85 86 /// EmitInstructions - Emit the last instruction in the vector and any other 87 /// instructions that are suitably similar to it. 88 static void EmitInstructions(std::vector<AsmWriterInst> &Insts, 89 raw_ostream &O) { 90 AsmWriterInst FirstInst = Insts.back(); 91 Insts.pop_back(); 92 93 std::vector<AsmWriterInst> SimilarInsts; 94 unsigned DifferingOperand = ~0; 95 for (unsigned i = Insts.size(); i != 0; --i) { 96 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 97 if (DiffOp != ~1U) { 98 if (DifferingOperand == ~0U) // First match! 99 DifferingOperand = DiffOp; 100 101 // If this differs in the same operand as the rest of the instructions in 102 // this class, move it to the SimilarInsts list. 103 if (DifferingOperand == DiffOp || DiffOp == ~0U) { 104 SimilarInsts.push_back(Insts[i-1]); 105 Insts.erase(Insts.begin()+i-1); 106 } 107 } 108 } 109 110 O << " case " << FirstInst.CGI->Namespace << "::" 111 << FirstInst.CGI->TheDef->getName() << ":\n"; 112 for (unsigned i = 0, e = SimilarInsts.size(); i != e; ++i) 113 O << " case " << SimilarInsts[i].CGI->Namespace << "::" 114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n"; 115 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 116 if (i != DifferingOperand) { 117 // If the operand is the same for all instructions, just print it. 118 O << " " << FirstInst.Operands[i].getCode(); 119 } else { 120 // If this is the operand that varies between all of the instructions, 121 // emit a switch for just this operand now. 122 O << " switch (MI->getOpcode()) {\n"; 123 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint; 124 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + 125 FirstInst.CGI->TheDef->getName(), 126 FirstInst.Operands[i])); 127 128 for (unsigned si = 0, e = SimilarInsts.size(); si != e; ++si) { 129 AsmWriterInst &AWI = SimilarInsts[si]; 130 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ 131 AWI.CGI->TheDef->getName(), 132 AWI.Operands[i])); 133 } 134 std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 135 while (!OpsToPrint.empty()) 136 PrintCases(OpsToPrint, O); 137 O << " }"; 138 } 139 O << "\n"; 140 } 141 O << " break;\n"; 142 } 143 144 void AsmWriterEmitter:: 145 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 146 std::vector<unsigned> &InstIdxs, 147 std::vector<unsigned> &InstOpsUsed) const { 148 InstIdxs.assign(NumberedInstructions->size(), ~0U); 149 150 // This vector parallels UniqueOperandCommands, keeping track of which 151 // instructions each case are used for. It is a comma separated string of 152 // enums. 153 std::vector<std::string> InstrsForCase; 154 InstrsForCase.resize(UniqueOperandCommands.size()); 155 InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 156 157 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 158 const AsmWriterInst *Inst = getAsmWriterInstByID(i); 159 if (!Inst) 160 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc. 161 162 std::string Command; 163 if (Inst->Operands.empty()) 164 continue; // Instruction already done. 165 166 Command = " " + Inst->Operands[0].getCode() + "\n"; 167 168 // Check to see if we already have 'Command' in UniqueOperandCommands. 169 // If not, add it. 170 bool FoundIt = false; 171 for (unsigned idx = 0, e = UniqueOperandCommands.size(); idx != e; ++idx) 172 if (UniqueOperandCommands[idx] == Command) { 173 InstIdxs[i] = idx; 174 InstrsForCase[idx] += ", "; 175 InstrsForCase[idx] += Inst->CGI->TheDef->getName(); 176 FoundIt = true; 177 break; 178 } 179 if (!FoundIt) { 180 InstIdxs[i] = UniqueOperandCommands.size(); 181 UniqueOperandCommands.push_back(Command); 182 InstrsForCase.push_back(Inst->CGI->TheDef->getName()); 183 184 // This command matches one operand so far. 185 InstOpsUsed.push_back(1); 186 } 187 } 188 189 // For each entry of UniqueOperandCommands, there is a set of instructions 190 // that uses it. If the next command of all instructions in the set are 191 // identical, fold it into the command. 192 for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size(); 193 CommandIdx != e; ++CommandIdx) { 194 195 for (unsigned Op = 1; ; ++Op) { 196 // Scan for the first instruction in the set. 197 std::vector<unsigned>::iterator NIT = 198 std::find(InstIdxs.begin(), InstIdxs.end(), CommandIdx); 199 if (NIT == InstIdxs.end()) break; // No commonality. 200 201 // If this instruction has no more operands, we isn't anything to merge 202 // into this command. 203 const AsmWriterInst *FirstInst = 204 getAsmWriterInstByID(NIT-InstIdxs.begin()); 205 if (!FirstInst || FirstInst->Operands.size() == Op) 206 break; 207 208 // Otherwise, scan to see if all of the other instructions in this command 209 // set share the operand. 210 bool AllSame = true; 211 212 for (NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx); 213 NIT != InstIdxs.end(); 214 NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) { 215 // Okay, found another instruction in this command set. If the operand 216 // matches, we're ok, otherwise bail out. 217 const AsmWriterInst *OtherInst = 218 getAsmWriterInstByID(NIT-InstIdxs.begin()); 219 220 if (!OtherInst || OtherInst->Operands.size() == Op || 221 OtherInst->Operands[Op] != FirstInst->Operands[Op]) { 222 AllSame = false; 223 break; 224 } 225 } 226 if (!AllSame) break; 227 228 // Okay, everything in this command set has the same next operand. Add it 229 // to UniqueOperandCommands and remember that it was consumed. 230 std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n"; 231 232 UniqueOperandCommands[CommandIdx] += Command; 233 InstOpsUsed[CommandIdx]++; 234 } 235 } 236 237 // Prepend some of the instructions each case is used for onto the case val. 238 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 239 std::string Instrs = InstrsForCase[i]; 240 if (Instrs.size() > 70) { 241 Instrs.erase(Instrs.begin()+70, Instrs.end()); 242 Instrs += "..."; 243 } 244 245 if (!Instrs.empty()) 246 UniqueOperandCommands[i] = " // " + Instrs + "\n" + 247 UniqueOperandCommands[i]; 248 } 249 } 250 251 252 static void UnescapeString(std::string &Str) { 253 for (unsigned i = 0; i != Str.size(); ++i) { 254 if (Str[i] == '\\' && i != Str.size()-1) { 255 switch (Str[i+1]) { 256 default: continue; // Don't execute the code after the switch. 257 case 'a': Str[i] = '\a'; break; 258 case 'b': Str[i] = '\b'; break; 259 case 'e': Str[i] = 27; break; 260 case 'f': Str[i] = '\f'; break; 261 case 'n': Str[i] = '\n'; break; 262 case 'r': Str[i] = '\r'; break; 263 case 't': Str[i] = '\t'; break; 264 case 'v': Str[i] = '\v'; break; 265 case '"': Str[i] = '\"'; break; 266 case '\'': Str[i] = '\''; break; 267 case '\\': Str[i] = '\\'; break; 268 } 269 // Nuke the second character. 270 Str.erase(Str.begin()+i+1); 271 } 272 } 273 } 274 275 /// EmitPrintInstruction - Generate the code for the "printInstruction" method 276 /// implementation. Destroys all instances of AsmWriterInst information, by 277 /// clearing the Instructions vector. 278 void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 279 Record *AsmWriter = Target.getAsmWriter(); 280 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 281 unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 282 283 O << 284 "/// printInstruction - This method is automatically generated by tablegen\n" 285 "/// from the instruction set description.\n" 286 "void " << Target.getName() << ClassName 287 << "::printInstruction(const MCInst *MI, " 288 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 289 << "raw_ostream &O) {\n"; 290 291 // Build an aggregate string, and build a table of offsets into it. 292 SequenceToOffsetTable<std::string> StringTable; 293 294 /// OpcodeInfo - This encodes the index of the string to use for the first 295 /// chunk of the output as well as indices used for operand printing. 296 /// To reduce the number of unhandled cases, we expand the size from 32-bit 297 /// to 32+16 = 48-bit. 298 std::vector<uint64_t> OpcodeInfo; 299 300 // Add all strings to the string table upfront so it can generate an optimized 301 // representation. 302 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 303 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; 304 if (AWI && 305 AWI->Operands[0].OperandType == 306 AsmWriterOperand::isLiteralTextOperand && 307 !AWI->Operands[0].Str.empty()) { 308 std::string Str = AWI->Operands[0].Str; 309 UnescapeString(Str); 310 StringTable.add(Str); 311 } 312 } 313 314 StringTable.layout(); 315 316 unsigned MaxStringIdx = 0; 317 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 318 AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions->at(i)]; 319 unsigned Idx; 320 if (!AWI) { 321 // Something not handled by the asmwriter printer. 322 Idx = ~0U; 323 } else if (AWI->Operands[0].OperandType != 324 AsmWriterOperand::isLiteralTextOperand || 325 AWI->Operands[0].Str.empty()) { 326 // Something handled by the asmwriter printer, but with no leading string. 327 Idx = StringTable.get(""); 328 } else { 329 std::string Str = AWI->Operands[0].Str; 330 UnescapeString(Str); 331 Idx = StringTable.get(Str); 332 MaxStringIdx = std::max(MaxStringIdx, Idx); 333 334 // Nuke the string from the operand list. It is now handled! 335 AWI->Operands.erase(AWI->Operands.begin()); 336 } 337 338 // Bias offset by one since we want 0 as a sentinel. 339 OpcodeInfo.push_back(Idx+1); 340 } 341 342 // Figure out how many bits we used for the string index. 343 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); 344 345 // To reduce code size, we compactify common instructions into a few bits 346 // in the opcode-indexed table. 347 unsigned BitsLeft = 64-AsmStrBits; 348 349 std::vector<std::vector<std::string>> TableDrivenOperandPrinters; 350 351 while (1) { 352 std::vector<std::string> UniqueOperandCommands; 353 std::vector<unsigned> InstIdxs; 354 std::vector<unsigned> NumInstOpsHandled; 355 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 356 NumInstOpsHandled); 357 358 // If we ran out of operands to print, we're done. 359 if (UniqueOperandCommands.empty()) break; 360 361 // Compute the number of bits we need to represent these cases, this is 362 // ceil(log2(numentries)). 363 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 364 365 // If we don't have enough bits for this operand, don't include it. 366 if (NumBits > BitsLeft) { 367 DEBUG(errs() << "Not enough bits to densely encode " << NumBits 368 << " more bits\n"); 369 break; 370 } 371 372 // Otherwise, we can include this in the initial lookup table. Add it in. 373 for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) 374 if (InstIdxs[i] != ~0U) { 375 OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft); 376 } 377 BitsLeft -= NumBits; 378 379 // Remove the info about this operand. 380 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 381 if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) 382 if (!Inst->Operands.empty()) { 383 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]]; 384 assert(NumOps <= Inst->Operands.size() && 385 "Can't remove this many ops!"); 386 Inst->Operands.erase(Inst->Operands.begin(), 387 Inst->Operands.begin()+NumOps); 388 } 389 } 390 391 // Remember the handlers for this set of operands. 392 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); 393 } 394 395 396 // We always emit at least one 32-bit table. A second table is emitted if 397 // more bits are needed. 398 O<<" static const uint32_t OpInfo[] = {\n"; 399 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 400 O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// " 401 << NumberedInstructions->at(i)->TheDef->getName() << "\n"; 402 } 403 // Add a dummy entry so the array init doesn't end with a comma. 404 O << " 0U\n"; 405 O << " };\n\n"; 406 407 if (BitsLeft < 32) { 408 // Add a second OpInfo table only when it is necessary. 409 // Adjust the type of the second table based on the number of bits needed. 410 O << " static const uint" 411 << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8") 412 << "_t OpInfo2[] = {\n"; 413 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) { 414 O << " " << (OpcodeInfo[i] >> 32) << "U,\t// " 415 << NumberedInstructions->at(i)->TheDef->getName() << "\n"; 416 } 417 // Add a dummy entry so the array init doesn't end with a comma. 418 O << " 0U\n"; 419 O << " };\n\n"; 420 } 421 422 // Emit the string itself. 423 O << " static const char AsmStrs[] = {\n"; 424 StringTable.emit(O, printChar); 425 O << " };\n\n"; 426 427 O << " O << \"\\t\";\n\n"; 428 429 O << " // Emit the opcode for the instruction.\n"; 430 if (BitsLeft < 32) { 431 // If we have two tables then we need to perform two lookups and combine 432 // the results into a single 64-bit value. 433 O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n" 434 << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n" 435 << " uint64_t Bits = (Bits2 << 32) | Bits1;\n"; 436 } else { 437 // If only one table is used we just need to perform a single lookup. 438 O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n"; 439 } 440 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 441 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 442 443 // Output the table driven operand information. 444 BitsLeft = 64-AsmStrBits; 445 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 446 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 447 448 // Compute the number of bits we need to represent these cases, this is 449 // ceil(log2(numentries)). 450 unsigned NumBits = Log2_32_Ceil(Commands.size()); 451 assert(NumBits <= BitsLeft && "consistency error"); 452 453 // Emit code to extract this field from Bits. 454 O << "\n // Fragment " << i << " encoded into " << NumBits 455 << " bits for " << Commands.size() << " unique commands.\n"; 456 457 if (Commands.size() == 2) { 458 // Emit two possibilitys with if/else. 459 O << " if ((Bits >> " 460 << (64-BitsLeft) << ") & " 461 << ((1 << NumBits)-1) << ") {\n" 462 << Commands[1] 463 << " } else {\n" 464 << Commands[0] 465 << " }\n\n"; 466 } else if (Commands.size() == 1) { 467 // Emit a single possibility. 468 O << Commands[0] << "\n\n"; 469 } else { 470 O << " switch ((Bits >> " 471 << (64-BitsLeft) << ") & " 472 << ((1 << NumBits)-1) << ") {\n" 473 << " default: llvm_unreachable(\"Invalid command number.\");\n"; 474 475 // Print out all the cases. 476 for (unsigned i = 0, e = Commands.size(); i != e; ++i) { 477 O << " case " << i << ":\n"; 478 O << Commands[i]; 479 O << " break;\n"; 480 } 481 O << " }\n\n"; 482 } 483 BitsLeft -= NumBits; 484 } 485 486 // Okay, delete instructions with no operand info left. 487 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { 488 // Entire instruction has been emitted? 489 AsmWriterInst &Inst = Instructions[i]; 490 if (Inst.Operands.empty()) { 491 Instructions.erase(Instructions.begin()+i); 492 --i; --e; 493 } 494 } 495 496 497 // Because this is a vector, we want to emit from the end. Reverse all of the 498 // elements in the vector. 499 std::reverse(Instructions.begin(), Instructions.end()); 500 501 502 // Now that we've emitted all of the operand info that fit into 32 bits, emit 503 // information for those instructions that are left. This is a less dense 504 // encoding, but we expect the main 32-bit table to handle the majority of 505 // instructions. 506 if (!Instructions.empty()) { 507 // Find the opcode # of inline asm. 508 O << " switch (MI->getOpcode()) {\n"; 509 while (!Instructions.empty()) 510 EmitInstructions(Instructions, O); 511 512 O << " }\n"; 513 O << " return;\n"; 514 } 515 516 O << "}\n"; 517 } 518 519 static const char *getMinimalTypeForRange(uint64_t Range) { 520 assert(Range < 0xFFFFFFFFULL && "Enum too large"); 521 if (Range > 0xFFFF) 522 return "uint32_t"; 523 if (Range > 0xFF) 524 return "uint16_t"; 525 return "uint8_t"; 526 } 527 528 static void 529 emitRegisterNameString(raw_ostream &O, StringRef AltName, 530 const std::deque<CodeGenRegister> &Registers) { 531 SequenceToOffsetTable<std::string> StringTable; 532 SmallVector<std::string, 4> AsmNames(Registers.size()); 533 unsigned i = 0; 534 for (const auto &Reg : Registers) { 535 std::string &AsmName = AsmNames[i++]; 536 537 // "NoRegAltName" is special. We don't need to do a lookup for that, 538 // as it's just a reference to the default register name. 539 if (AltName == "" || AltName == "NoRegAltName") { 540 AsmName = Reg.TheDef->getValueAsString("AsmName"); 541 if (AsmName.empty()) 542 AsmName = Reg.getName(); 543 } else { 544 // Make sure the register has an alternate name for this index. 545 std::vector<Record*> AltNameList = 546 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 547 unsigned Idx = 0, e; 548 for (e = AltNameList.size(); 549 Idx < e && (AltNameList[Idx]->getName() != AltName); 550 ++Idx) 551 ; 552 // If the register has an alternate name for this index, use it. 553 // Otherwise, leave it empty as an error flag. 554 if (Idx < e) { 555 std::vector<std::string> AltNames = 556 Reg.TheDef->getValueAsListOfStrings("AltNames"); 557 if (AltNames.size() <= Idx) 558 PrintFatalError(Reg.TheDef->getLoc(), 559 "Register definition missing alt name for '" + 560 AltName + "'."); 561 AsmName = AltNames[Idx]; 562 } 563 } 564 StringTable.add(AsmName); 565 } 566 567 StringTable.layout(); 568 O << " static const char AsmStrs" << AltName << "[] = {\n"; 569 StringTable.emit(O, printChar); 570 O << " };\n\n"; 571 572 O << " static const " << getMinimalTypeForRange(StringTable.size()-1) 573 << " RegAsmOffset" << AltName << "[] = {"; 574 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 575 if ((i % 14) == 0) 576 O << "\n "; 577 O << StringTable.get(AsmNames[i]) << ", "; 578 } 579 O << "\n };\n" 580 << "\n"; 581 } 582 583 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 584 Record *AsmWriter = Target.getAsmWriter(); 585 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 586 const auto &Registers = Target.getRegBank().getRegisters(); 587 std::vector<Record*> AltNameIndices = Target.getRegAltNameIndices(); 588 bool hasAltNames = AltNameIndices.size() > 1; 589 590 O << 591 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 592 "/// from the register set description. This returns the assembler name\n" 593 "/// for the specified register.\n" 594 "const char *" << Target.getName() << ClassName << "::"; 595 if (hasAltNames) 596 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 597 else 598 O << "getRegisterName(unsigned RegNo) {\n"; 599 O << " assert(RegNo && RegNo < " << (Registers.size()+1) 600 << " && \"Invalid register number!\");\n" 601 << "\n"; 602 603 if (hasAltNames) { 604 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) 605 emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers); 606 } else 607 emitRegisterNameString(O, "", Registers); 608 609 if (hasAltNames) { 610 O << " switch(AltIdx) {\n" 611 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; 612 for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) { 613 std::string Namespace = AltNameIndices[1]->getValueAsString("Namespace"); 614 std::string AltName(AltNameIndices[i]->getName()); 615 O << " case " << Namespace << "::" << AltName << ":\n" 616 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" 617 << AltName << "[RegNo-1]) &&\n" 618 << " \"Invalid alt name index for register!\");\n" 619 << " return AsmStrs" << AltName << "+RegAsmOffset" 620 << AltName << "[RegNo-1];\n"; 621 } 622 O << " }\n"; 623 } else { 624 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 625 << " \"Invalid alt name index for register!\");\n" 626 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; 627 } 628 O << "}\n"; 629 } 630 631 namespace { 632 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if 633 // they both have the same conditionals. In which case, we cannot print out the 634 // alias for that pattern. 635 class IAPrinter { 636 std::vector<std::string> Conds; 637 std::map<StringRef, std::pair<int, int>> OpMap; 638 SmallVector<Record*, 4> ReqFeatures; 639 640 std::string Result; 641 std::string AsmString; 642 public: 643 IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {} 644 645 void addCond(const std::string &C) { Conds.push_back(C); } 646 647 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { 648 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 649 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && 650 "Idx out of range"); 651 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 652 } 653 654 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } 655 int getOpIndex(StringRef Op) { return OpMap[Op].first; } 656 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; } 657 658 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start, 659 StringRef::iterator End) { 660 StringRef::iterator I = Start; 661 StringRef::iterator Next; 662 if (*I == '{') { 663 // ${some_name} 664 Start = ++I; 665 while (I != End && *I != '}') 666 ++I; 667 Next = I; 668 // eat the final '}' 669 if (Next != End) 670 ++Next; 671 } else { 672 // $name, just eat the usual suspects. 673 while (I != End && 674 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || 675 (*I >= '0' && *I <= '9') || *I == '_')) 676 ++I; 677 Next = I; 678 } 679 680 return std::make_pair(StringRef(Start, I - Start), Next); 681 } 682 683 void print(raw_ostream &O) { 684 if (Conds.empty() && ReqFeatures.empty()) { 685 O.indent(6) << "return true;\n"; 686 return; 687 } 688 689 O << "if ("; 690 691 for (std::vector<std::string>::iterator 692 I = Conds.begin(), E = Conds.end(); I != E; ++I) { 693 if (I != Conds.begin()) { 694 O << " &&\n"; 695 O.indent(8); 696 } 697 698 O << *I; 699 } 700 701 O << ") {\n"; 702 O.indent(6) << "// " << Result << "\n"; 703 704 // Directly mangle mapped operands into the string. Each operand is 705 // identified by a '$' sign followed by a byte identifying the number of the 706 // operand. We add one to the index to avoid zero bytes. 707 StringRef ASM(AsmString); 708 SmallString<128> OutString; 709 raw_svector_ostream OS(OutString); 710 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { 711 OS << *I; 712 if (*I == '$') { 713 StringRef Name; 714 std::tie(Name, I) = parseName(++I, E); 715 assert(isOpMapped(Name) && "Unmapped operand!"); 716 717 int OpIndex, PrintIndex; 718 std::tie(OpIndex, PrintIndex) = getOpData(Name); 719 if (PrintIndex == -1) { 720 // Can use the default printOperand route. 721 OS << format("\\x%02X", (unsigned char)OpIndex + 1); 722 } else 723 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand 724 // number, and which of our pre-detected Methods to call. 725 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); 726 } else { 727 ++I; 728 } 729 } 730 OS.flush(); 731 732 // Emit the string. 733 O.indent(6) << "AsmString = \"" << OutString << "\";\n"; 734 735 O.indent(6) << "break;\n"; 736 O.indent(4) << '}'; 737 } 738 739 bool operator==(const IAPrinter &RHS) { 740 if (Conds.size() != RHS.Conds.size()) 741 return false; 742 743 unsigned Idx = 0; 744 for (std::vector<std::string>::iterator 745 I = Conds.begin(), E = Conds.end(); I != E; ++I) 746 if (*I != RHS.Conds[Idx++]) 747 return false; 748 749 return true; 750 } 751 }; 752 753 } // end anonymous namespace 754 755 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { 756 std::string FlatAsmString = 757 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant); 758 AsmString = FlatAsmString; 759 760 return AsmString.count(' ') + AsmString.count('\t'); 761 } 762 763 namespace { 764 struct AliasPriorityComparator { 765 typedef std::pair<CodeGenInstAlias *, int> ValueType; 766 bool operator()(const ValueType &LHS, const ValueType &RHS) { 767 if (LHS.second == RHS.second) { 768 // We don't actually care about the order, but for consistency it 769 // shouldn't depend on pointer comparisons. 770 return LHS.first->TheDef->getName() < RHS.first->TheDef->getName(); 771 } 772 773 // Aliases with larger priorities should be considered first. 774 return LHS.second > RHS.second; 775 } 776 }; 777 } 778 779 780 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { 781 Record *AsmWriter = Target.getAsmWriter(); 782 783 O << "\n#ifdef PRINT_ALIAS_INSTR\n"; 784 O << "#undef PRINT_ALIAS_INSTR\n\n"; 785 786 ////////////////////////////// 787 // Gather information about aliases we need to print 788 ////////////////////////////// 789 790 // Emit the method that prints the alias instruction. 791 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 792 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 793 unsigned PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 794 795 std::vector<Record*> AllInstAliases = 796 Records.getAllDerivedDefinitions("InstAlias"); 797 798 // Create a map from the qualified name to a list of potential matches. 799 typedef std::set<std::pair<CodeGenInstAlias*, int>, AliasPriorityComparator> 800 AliasWithPriority; 801 std::map<std::string, AliasWithPriority> AliasMap; 802 for (std::vector<Record*>::iterator 803 I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { 804 CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Variant, Target); 805 const Record *R = *I; 806 int Priority = R->getValueAsInt("EmitPriority"); 807 if (Priority < 1) 808 continue; // Aliases with priority 0 are never emitted. 809 810 const DagInit *DI = R->getValueAsDag("ResultInst"); 811 const DefInit *Op = cast<DefInit>(DI->getOperator()); 812 AliasMap[getQualifiedName(Op->getDef())].insert(std::make_pair(Alias, 813 Priority)); 814 } 815 816 // A map of which conditions need to be met for each instruction operand 817 // before it can be matched to the mnemonic. 818 std::map<std::string, std::vector<IAPrinter*> > IAPrinterMap; 819 820 // A list of MCOperandPredicates for all operands in use, and the reverse map 821 std::vector<const Record*> MCOpPredicates; 822 DenseMap<const Record*, unsigned> MCOpPredicateMap; 823 824 for (auto &Aliases : AliasMap) { 825 for (auto &Alias : Aliases.second) { 826 const CodeGenInstAlias *CGA = Alias.first; 827 unsigned LastOpNo = CGA->ResultInstOperandIndex.size(); 828 unsigned NumResultOps = 829 CountNumOperands(CGA->ResultInst->AsmString, Variant); 830 831 // Don't emit the alias if it has more operands than what it's aliasing. 832 if (NumResultOps < CountNumOperands(CGA->AsmString, Variant)) 833 continue; 834 835 IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), 836 CGA->AsmString); 837 838 unsigned NumMIOps = 0; 839 for (auto &Operand : CGA->ResultOperands) 840 NumMIOps += Operand.getMINumOperands(); 841 842 std::string Cond; 843 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); 844 IAP->addCond(Cond); 845 846 bool CantHandle = false; 847 848 unsigned MIOpNum = 0; 849 for (unsigned i = 0, e = LastOpNo; i != e; ++i) { 850 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; 851 852 const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; 853 854 switch (RO.Kind) { 855 case CodeGenInstAlias::ResultOperand::K_Record: { 856 const Record *Rec = RO.getRecord(); 857 StringRef ROName = RO.getName(); 858 int PrintMethodIdx = -1; 859 860 // These two may have a PrintMethod, which we want to record (if it's 861 // the first time we've seen it) and provide an index for the aliasing 862 // code to use. 863 if (Rec->isSubClassOf("RegisterOperand") || 864 Rec->isSubClassOf("Operand")) { 865 std::string PrintMethod = Rec->getValueAsString("PrintMethod"); 866 if (PrintMethod != "" && PrintMethod != "printOperand") { 867 PrintMethodIdx = std::find(PrintMethods.begin(), 868 PrintMethods.end(), PrintMethod) - 869 PrintMethods.begin(); 870 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size()) 871 PrintMethods.push_back(PrintMethod); 872 } 873 } 874 875 if (Rec->isSubClassOf("RegisterOperand")) 876 Rec = Rec->getValueAsDef("RegClass"); 877 if (Rec->isSubClassOf("RegisterClass")) { 878 IAP->addCond(Op + ".isReg()"); 879 880 if (!IAP->isOpMapped(ROName)) { 881 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); 882 Record *R = CGA->ResultOperands[i].getRecord(); 883 if (R->isSubClassOf("RegisterOperand")) 884 R = R->getValueAsDef("RegClass"); 885 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + 886 R->getName() + "RegClassID)" 887 ".contains(" + Op + ".getReg())"; 888 } else { 889 Cond = Op + ".getReg() == MI->getOperand(" + 890 llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; 891 } 892 } else { 893 // Assume all printable operands are desired for now. This can be 894 // overridden in the InstAlias instantiation if necessary. 895 IAP->addOperand(ROName, MIOpNum, PrintMethodIdx); 896 897 // There might be an additional predicate on the MCOperand 898 unsigned Entry = MCOpPredicateMap[Rec]; 899 if (!Entry) { 900 if (!Rec->isValueUnset("MCOperandPredicate")) { 901 MCOpPredicates.push_back(Rec); 902 Entry = MCOpPredicates.size(); 903 MCOpPredicateMap[Rec] = Entry; 904 } else 905 break; // No conditions on this operand at all 906 } 907 Cond = Target.getName() + ClassName + "ValidateMCOperand(" + 908 Op + ", " + llvm::utostr(Entry) + ")"; 909 } 910 // for all subcases of ResultOperand::K_Record: 911 IAP->addCond(Cond); 912 break; 913 } 914 case CodeGenInstAlias::ResultOperand::K_Imm: { 915 // Just because the alias has an immediate result, doesn't mean the 916 // MCInst will. An MCExpr could be present, for example. 917 IAP->addCond(Op + ".isImm()"); 918 919 Cond = Op + ".getImm() == " 920 + llvm::utostr(CGA->ResultOperands[i].getImm()); 921 IAP->addCond(Cond); 922 break; 923 } 924 case CodeGenInstAlias::ResultOperand::K_Reg: 925 // If this is zero_reg, something's playing tricks we're not 926 // equipped to handle. 927 if (!CGA->ResultOperands[i].getRegister()) { 928 CantHandle = true; 929 break; 930 } 931 932 Cond = Op + ".getReg() == " + Target.getName() + 933 "::" + CGA->ResultOperands[i].getRegister()->getName(); 934 IAP->addCond(Cond); 935 break; 936 } 937 938 if (!IAP) break; 939 MIOpNum += RO.getMINumOperands(); 940 } 941 942 if (CantHandle) continue; 943 IAPrinterMap[Aliases.first].push_back(IAP); 944 } 945 } 946 947 ////////////////////////////// 948 // Write out the printAliasInstr function 949 ////////////////////////////// 950 951 std::string Header; 952 raw_string_ostream HeaderO(Header); 953 954 HeaderO << "bool " << Target.getName() << ClassName 955 << "::printAliasInstr(const MCInst" 956 << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 957 << "raw_ostream &OS) {\n"; 958 959 std::string Cases; 960 raw_string_ostream CasesO(Cases); 961 962 for (std::map<std::string, std::vector<IAPrinter*> >::iterator 963 I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { 964 std::vector<IAPrinter*> &IAPs = I->second; 965 std::vector<IAPrinter*> UniqueIAPs; 966 967 for (std::vector<IAPrinter*>::iterator 968 II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) { 969 IAPrinter *LHS = *II; 970 bool IsDup = false; 971 for (std::vector<IAPrinter*>::iterator 972 III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) { 973 IAPrinter *RHS = *III; 974 if (LHS != RHS && *LHS == *RHS) { 975 IsDup = true; 976 break; 977 } 978 } 979 980 if (!IsDup) UniqueIAPs.push_back(LHS); 981 } 982 983 if (UniqueIAPs.empty()) continue; 984 985 CasesO.indent(2) << "case " << I->first << ":\n"; 986 987 for (std::vector<IAPrinter*>::iterator 988 II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { 989 IAPrinter *IAP = *II; 990 CasesO.indent(4); 991 IAP->print(CasesO); 992 CasesO << '\n'; 993 } 994 995 CasesO.indent(4) << "return false;\n"; 996 } 997 998 if (CasesO.str().empty()) { 999 O << HeaderO.str(); 1000 O << " return false;\n"; 1001 O << "}\n\n"; 1002 O << "#endif // PRINT_ALIAS_INSTR\n"; 1003 return; 1004 } 1005 1006 if (!MCOpPredicates.empty()) 1007 O << "static bool " << Target.getName() << ClassName 1008 << "ValidateMCOperand(\n" 1009 << " const MCOperand &MCOp, unsigned PredicateIndex);\n"; 1010 1011 O << HeaderO.str(); 1012 O.indent(2) << "const char *AsmString;\n"; 1013 O.indent(2) << "switch (MI->getOpcode()) {\n"; 1014 O.indent(2) << "default: return false;\n"; 1015 O << CasesO.str(); 1016 O.indent(2) << "}\n\n"; 1017 1018 // Code that prints the alias, replacing the operands with the ones from the 1019 // MCInst. 1020 O << " unsigned I = 0;\n"; 1021 O << " while (AsmString[I] != ' ' && AsmString[I] != '\t' &&\n"; 1022 O << " AsmString[I] != '\\0')\n"; 1023 O << " ++I;\n"; 1024 O << " OS << '\\t' << StringRef(AsmString, I);\n"; 1025 1026 O << " if (AsmString[I] != '\\0') {\n"; 1027 O << " OS << '\\t';\n"; 1028 O << " do {\n"; 1029 O << " if (AsmString[I] == '$') {\n"; 1030 O << " ++I;\n"; 1031 O << " if (AsmString[I] == (char)0xff) {\n"; 1032 O << " ++I;\n"; 1033 O << " int OpIdx = AsmString[I++] - 1;\n"; 1034 O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; 1035 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; 1036 O << (PassSubtarget ? "STI, " : ""); 1037 O << "OS);\n"; 1038 O << " } else\n"; 1039 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; 1040 O << (PassSubtarget ? "STI, " : ""); 1041 O << "OS);\n"; 1042 O << " } else {\n"; 1043 O << " OS << AsmString[I++];\n"; 1044 O << " }\n"; 1045 O << " } while (AsmString[I] != '\\0');\n"; 1046 O << " }\n\n"; 1047 1048 O << " return true;\n"; 1049 O << "}\n\n"; 1050 1051 ////////////////////////////// 1052 // Write out the printCustomAliasOperand function 1053 ////////////////////////////// 1054 1055 O << "void " << Target.getName() << ClassName << "::" 1056 << "printCustomAliasOperand(\n" 1057 << " const MCInst *MI, unsigned OpIdx,\n" 1058 << " unsigned PrintMethodIdx,\n" 1059 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") 1060 << " raw_ostream &OS) {\n"; 1061 if (PrintMethods.empty()) 1062 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; 1063 else { 1064 O << " switch (PrintMethodIdx) {\n" 1065 << " default:\n" 1066 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" 1067 << " break;\n"; 1068 1069 for (unsigned i = 0; i < PrintMethods.size(); ++i) { 1070 O << " case " << i << ":\n" 1071 << " " << PrintMethods[i] << "(MI, OpIdx, " 1072 << (PassSubtarget ? "STI, " : "") << "OS);\n" 1073 << " break;\n"; 1074 } 1075 O << " }\n"; 1076 } 1077 O << "}\n\n"; 1078 1079 if (!MCOpPredicates.empty()) { 1080 O << "static bool " << Target.getName() << ClassName 1081 << "ValidateMCOperand(\n" 1082 << " const MCOperand &MCOp, unsigned PredicateIndex) {\n" 1083 << " switch (PredicateIndex) {\n" 1084 << " default:\n" 1085 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n" 1086 << " break;\n"; 1087 1088 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) { 1089 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate"); 1090 if (StringInit *SI = dyn_cast<StringInit>(MCOpPred)) { 1091 O << " case " << i + 1 << ": {\n" 1092 << SI->getValue() << "\n" 1093 << " }\n"; 1094 } else 1095 llvm_unreachable("Unexpected MCOperandPredicate field!"); 1096 } 1097 O << " }\n" 1098 << "}\n\n"; 1099 } 1100 1101 O << "#endif // PRINT_ALIAS_INSTR\n"; 1102 } 1103 1104 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1105 Record *AsmWriter = Target.getAsmWriter(); 1106 for (const CodeGenInstruction *I : Target.instructions()) 1107 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") 1108 Instructions.push_back( 1109 AsmWriterInst(*I, AsmWriter->getValueAsInt("Variant"), 1110 AsmWriter->getValueAsInt("PassSubtarget"))); 1111 1112 // Get the instruction numbering. 1113 NumberedInstructions = &Target.getInstructionsByEnumValue(); 1114 1115 // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not 1116 // all machine instructions are necessarily being printed, so there may be 1117 // target instructions not in this map. 1118 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) 1119 CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); 1120 } 1121 1122 void AsmWriterEmitter::run(raw_ostream &O) { 1123 EmitPrintInstruction(O); 1124 EmitGetRegisterName(O); 1125 EmitPrintAliasInstruction(O); 1126 } 1127 1128 1129 namespace llvm { 1130 1131 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { 1132 emitSourceFileHeader("Assembly Writer Source Fragment", OS); 1133 AsmWriterEmitter(RK).run(OS); 1134 } 1135 1136 } // End llvm namespace 1137