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Searched
refs:OUT_BATCH
(Results
1 - 25
of
54
) sorted by null
1
2
3
/external/mesa3d/src/mesa/drivers/dri/i965/
gen7_disable.c
38
OUT_BATCH
(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
39
OUT_BATCH
(0);
40
OUT_BATCH
(0);
41
OUT_BATCH
(0);
42
OUT_BATCH
(0);
43
OUT_BATCH
(0);
44
OUT_BATCH
(0);
48
OUT_BATCH
(_3DSTATE_GS << 16 | (7 - 2));
49
OUT_BATCH
(0); /* prog_bo */
50
OUT_BATCH
((0 << GEN6_GS_SAMPLER_COUNT_SHIFT)
[
all
...]
gen6_gs_state.c
40
OUT_BATCH
(_3DSTATE_CONSTANT_GS << 16 | (5 - 2));
41
OUT_BATCH
(0);
42
OUT_BATCH
(0);
43
OUT_BATCH
(0);
44
OUT_BATCH
(0);
49
OUT_BATCH
(_3DSTATE_GS << 16 | (7 - 2));
50
OUT_BATCH
(brw->gs.prog_offset);
51
OUT_BATCH
(GEN6_GS_SPF_MODE | GEN6_GS_VECTOR_MASK_ENABLE);
52
OUT_BATCH
(0); /* no scratch space */
53
OUT_BATCH
((2 << GEN6_GS_DISPATCH_START_GRF_SHIFT)
[
all
...]
gen7_vs_state.c
44
OUT_BATCH
(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
45
OUT_BATCH
(brw->vs.bind_bo_offset);
50
OUT_BATCH
(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2));
51
OUT_BATCH
(brw->sampler.offset);
57
OUT_BATCH
(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
58
OUT_BATCH
(0);
59
OUT_BATCH
(0);
60
OUT_BATCH
(0);
61
OUT_BATCH
(0);
62
OUT_BATCH
(0)
[
all
...]
gen6_sampler_state.c
39
OUT_BATCH
(_3DSTATE_SAMPLER_STATE_POINTERS << 16 |
44
OUT_BATCH
(brw->sampler.offset); /* VS */
45
OUT_BATCH
(0); /* GS */
46
OUT_BATCH
(brw->sampler.offset);
gen7_wm_state.c
94
OUT_BATCH
(_3DSTATE_WM << 16 | (3 - 2));
95
OUT_BATCH
(dw1);
96
OUT_BATCH
(dw2);
123
OUT_BATCH
(_3DSTATE_BINDING_TABLE_POINTERS_PS << 16 | (2 - 2));
124
OUT_BATCH
(brw->wm.bind_bo_offset);
129
OUT_BATCH
(_3DSTATE_SAMPLER_STATE_POINTERS_PS << 16 | (2 - 2));
130
OUT_BATCH
(brw->sampler.offset);
137
OUT_BATCH
(_3DSTATE_CONSTANT_PS << 16 | (7 - 2));
138
OUT_BATCH
(0);
139
OUT_BATCH
(0)
[
all
...]
gen7_misc_state.c
147
OUT_BATCH
(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
148
OUT_BATCH
(dw1);
149
OUT_BATCH
(0);
150
OUT_BATCH
(dw3);
151
OUT_BATCH
(0);
152
OUT_BATCH
(tile_x | (tile_y << 16));
153
OUT_BATCH
(0);
191
OUT_BATCH
(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2));
192
OUT_BATCH
(((region->pitch * region->cpp) - 1) |
201
OUT_BATCH
((((drb->Base.Base.Width + tile_x) - 1) << 4)
[
all
...]
gen6_blorp.cpp
99
OUT_BATCH
(brw->CMD_PIPELINE_SELECT << 16);
124
OUT_BATCH
(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2));
125
OUT_BATCH
(1); /* GeneralStateBaseAddressModifyEnable */
131
OUT_BATCH
(1); /* IndirectObjectBaseAddress */
136
OUT_BATCH
(1); /* InstructionBaseAddress */
138
OUT_BATCH
(1); /* GeneralStateUpperBound */
144
OUT_BATCH
(0xfffff001);
145
OUT_BATCH
(1); /* IndirectObjectUpperBound*/
146
OUT_BATCH
(1); /* InstructionAccessUpperBound */
214
OUT_BATCH
((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2))
[
all
...]
gen7_cc_state.c
37
OUT_BATCH
(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
38
OUT_BATCH
(brw->cc.state_offset | 1);
57
OUT_BATCH
(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
58
OUT_BATCH
(brw->cc.blend_state_offset | 1);
77
OUT_BATCH
(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
78
OUT_BATCH
(brw->cc.depth_stencil_state_offset | 1);
gen7_urb.c
58
OUT_BATCH
(_3DSTATE_PUSH_CONSTANT_ALLOC_VS << 16 | (2 - 2));
59
OUT_BATCH
(8);
63
OUT_BATCH
(_3DSTATE_PUSH_CONSTANT_ALLOC_PS << 16 | (2 - 2));
64
OUT_BATCH
(8 | 8 << GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
114
OUT_BATCH
(_3DSTATE_URB_VS << 16 | (2 - 2));
115
OUT_BATCH
(nr_vs_entries |
122
OUT_BATCH
(_3DSTATE_URB_GS << 16 | (2 - 2));
123
OUT_BATCH
((0 << GEN7_URB_ENTRY_SIZE_SHIFT) |
128
OUT_BATCH
(_3DSTATE_URB_HS << 16 | (2 - 2));
129
OUT_BATCH
((0 << GEN7_URB_ENTRY_SIZE_SHIFT)
[
all
...]
brw_misc_state.c
52
OUT_BATCH
(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2));
53
OUT_BATCH
(0); /* xmin, ymin */
54
OUT_BATCH
(((ctx->DrawBuffer->Width - 1) & 0xffff) |
56
OUT_BATCH
(0);
81
OUT_BATCH
(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2));
82
OUT_BATCH
(brw->vs.bind_bo_offset);
83
OUT_BATCH
(0); /* gs */
84
OUT_BATCH
(0); /* clip */
85
OUT_BATCH
(0); /* sf */
86
OUT_BATCH
(brw->wm.bind_bo_offset)
[
all
...]
gen7_blorp.cpp
73
OUT_BATCH
(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2));
74
OUT_BATCH
(cc_blend_state_offset | 1);
88
OUT_BATCH
(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2));
89
OUT_BATCH
(cc_state_offset | 1);
108
OUT_BATCH
(_3DSTATE_VIEWPORT_STATE_POINTERS_CC << 16 | (2 - 2));
109
OUT_BATCH
(cc_vp_offset);
126
OUT_BATCH
(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2));
127
OUT_BATCH
(depthstencil_offset | 1);
289
OUT_BATCH
(_3DSTATE_HS << 16 | (7 - 2));
290
OUT_BATCH
(0)
[
all
...]
gen6_vs_state.c
148
OUT_BATCH
(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
149
OUT_BATCH
(0);
150
OUT_BATCH
(0);
151
OUT_BATCH
(0);
152
OUT_BATCH
(0);
156
OUT_BATCH
(_3DSTATE_CONSTANT_VS << 16 |
162
OUT_BATCH
(brw->vs.push_const_offset +
164
OUT_BATCH
(0);
165
OUT_BATCH
(0);
166
OUT_BATCH
(0)
[
all
...]
gen6_multisample_state.c
104
OUT_BATCH
(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
105
OUT_BATCH
(MS_PIXEL_LOCATION_CENTER | number_of_multisamples);
106
OUT_BATCH
(sample_positions_3210);
108
OUT_BATCH
(sample_positions_7654);
124
OUT_BATCH
(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2));
130
OUT_BATCH
(coverage_bits);
132
OUT_BATCH
(1);
gen6_clip_state.c
70
OUT_BATCH
(_3DSTATE_CLIP << 16 | (4 - 2));
71
OUT_BATCH
(GEN6_CLIP_STATISTICS_ENABLE);
72
OUT_BATCH
(GEN6_CLIP_ENABLE |
80
OUT_BATCH
(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
gen6_wm_state.c
108
OUT_BATCH
(_3DSTATE_CONSTANT_PS << 16 | (5 - 2));
109
OUT_BATCH
(0);
110
OUT_BATCH
(0);
111
OUT_BATCH
(0);
112
OUT_BATCH
(0);
116
OUT_BATCH
(_3DSTATE_CONSTANT_PS << 16 |
122
OUT_BATCH
(brw->wm.push_const_offset +
125
OUT_BATCH
(0);
126
OUT_BATCH
(0);
127
OUT_BATCH
(0)
[
all
...]
gen7_clip_state.c
97
OUT_BATCH
(_3DSTATE_CLIP << 16 | (4 - 2));
98
OUT_BATCH
(dw1);
99
OUT_BATCH
(GEN6_CLIP_ENABLE |
107
OUT_BATCH
(U_FIXED(0.125, 3) << GEN6_CLIP_MIN_POINT_WIDTH_SHIFT |
gen7_sol_state.c
67
OUT_BATCH
(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
68
OUT_BATCH
((i << SO_BUFFER_INDEX_SHIFT));
69
OUT_BATCH
(0);
70
OUT_BATCH
(0);
92
OUT_BATCH
(_3DSTATE_SO_BUFFER << 16 | (4 - 2));
93
OUT_BATCH
((i << SO_BUFFER_INDEX_SHIFT) | stride);
162
OUT_BATCH
(_3DSTATE_SO_DECL_LIST << 16 |
165
OUT_BATCH
((buffer_mask << SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT) |
170
OUT_BATCH
((linked_xfb_info->NumOutputs << SO_NUM_ENTRIES_0_SHIFT) |
176
OUT_BATCH
(so_decl[i])
[
all
...]
brw_queryobj.c
62
OUT_BATCH
(_3DSTATE_PIPE_CONTROL | (4 - 2));
63
OUT_BATCH
(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD);
64
OUT_BATCH
(0);
65
OUT_BATCH
(0);
70
OUT_BATCH
(_3DSTATE_PIPE_CONTROL | (5 - 2));
71
OUT_BATCH
(PIPE_CONTROL_WRITE_TIMESTAMP);
76
OUT_BATCH
(0);
77
OUT_BATCH
(0);
81
OUT_BATCH
(_3DSTATE_PIPE_CONTROL | (4 - 2) |
87
OUT_BATCH
(0)
[
all
...]
/external/mesa3d/src/gallium/drivers/i915/
i915_blit.c
78
OUT_BATCH
(CMD);
79
OUT_BATCH
(BR13);
80
OUT_BATCH
((y << 16) | x);
81
OUT_BATCH
(((y + h) << 16) | (x + w));
83
OUT_BATCH
(color);
150
OUT_BATCH
(CMD);
151
OUT_BATCH
(BR13);
152
OUT_BATCH
((dst_y << 16) | dst_x);
153
OUT_BATCH
((dst_y2 << 16) | dst_x2);
155
OUT_BATCH
((src_y << 16) | src_x)
[
all
...]
i915_clear.c
134
OUT_BATCH
(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
136
OUT_BATCH
(_3DSTATE_CLEAR_PARAMETERS);
137
OUT_BATCH
(CLEARPARAM_WRITE_COLOR | CLEARPARAM_CLEAR_RECT);
139
OUT_BATCH
(clear_color);
140
OUT_BATCH
(clear_depth);
142
OUT_BATCH
(clear_color8888);
144
OUT_BATCH
(clear_stencil);
146
OUT_BATCH
(_3DPRIMITIVE | PRIM3D_CLEAR_RECT | 5);
154
OUT_BATCH
(_3DSTATE_CLEAR_PARAMETERS);
155
OUT_BATCH
((clear_params & ~CLEARPARAM_WRITE_COLOR)
[
all
...]
i915_prim_emit.c
83
OUT_BATCH
( fui(attrib[0]) );
87
OUT_BATCH
( fui(attrib[0]) );
88
OUT_BATCH
( fui(attrib[1]) );
92
OUT_BATCH
( fui(attrib[0]) );
93
OUT_BATCH
( fui(attrib[1]) );
94
OUT_BATCH
( fui(attrib[2]) );
98
OUT_BATCH
( fui(attrib[0]) );
99
OUT_BATCH
( fui(attrib[1]) );
100
OUT_BATCH
( fui(attrib[2]) );
101
OUT_BATCH
( fui(attrib[3]) )
[
all
...]
i915_state_emit.c
68
OUT_BATCH
(MI_FLUSH | FLUSH_MAP_CACHE);
70
OUT_BATCH
(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE);
143
OUT_BATCH
(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
151
OUT_BATCH
(0);
169
OUT_BATCH
(imm);
171
OUT_BATCH
(i915->current.immediate[i]);
189
OUT_BATCH
(i915->current.dynamic[i]);
221
OUT_BATCH
(_3DSTATE_BUF_INFO_CMD);
222
OUT_BATCH
(i915->current.cbuf_flags);
231
OUT_BATCH
(_3DSTATE_BUF_INFO_CMD)
[
all
...]
/external/mesa3d/src/mesa/drivers/dri/intel/
intel_batchbuffer.c
383
OUT_BATCH
(_3DSTATE_PIPE_CONTROL | (4 - 2));
384
OUT_BATCH
(PIPE_CONTROL_DEPTH_STALL);
385
OUT_BATCH
(0); /* address */
386
OUT_BATCH
(0); /* write data */
390
OUT_BATCH
(_3DSTATE_PIPE_CONTROL | (4 - 2));
391
OUT_BATCH
(PIPE_CONTROL_DEPTH_CACHE_FLUSH);
392
OUT_BATCH
(0); /* address */
393
OUT_BATCH
(0); /* write data */
397
OUT_BATCH
(_3DSTATE_PIPE_CONTROL | (4 - 2));
398
OUT_BATCH
(PIPE_CONTROL_DEPTH_STALL)
[
all
...]
intel_blit.c
200
OUT_BATCH
(CMD);
201
OUT_BATCH
(BR13 | (uint16_t)dst_pitch);
202
OUT_BATCH
((dst_y << 16) | dst_x);
203
OUT_BATCH
((dst_y2 << 16) | dst_x2);
207
OUT_BATCH
((src_y << 16) | src_x);
208
OUT_BATCH
((uint16_t)src_pitch);
374
OUT_BATCH
(CMD);
375
OUT_BATCH
(BR13);
376
OUT_BATCH
((y1 << 16) | x1);
377
OUT_BATCH
((y2 << 16) | x2)
[
all
...]
/external/mesa3d/src/mesa/drivers/dri/radeon/
radeon_ioctl.c
104
OUT_BATCH
(CP_PACKET0(RADEON_PP_CNTL, 0));
105
OUT_BATCH
(rmesa->hw.ctx.cmd[CTX_PP_CNTL] | RADEON_SCISSOR_ENABLE);
106
OUT_BATCH
(CP_PACKET0(RADEON_RE_TOP_LEFT, 0));
107
OUT_BATCH
((rmesa->radeon.state.scissor.rect.y1 << 16) |
109
OUT_BATCH
(CP_PACKET0(RADEON_RE_WIDTH_HEIGHT, 0));
110
OUT_BATCH
(((rmesa->radeon.state.scissor.rect.y2) << 16) |
115
OUT_BATCH
(CP_PACKET0(RADEON_PP_CNTL, 0));
116
OUT_BATCH
(rmesa->hw.ctx.cmd[CTX_PP_CNTL] & ~RADEON_SCISSOR_ENABLE);
139
OUT_BATCH
(rmesa->ioctl.vertex_offset);
141
OUT_BATCH
(vertex_nr)
[
all
...]
Completed in 1294 milliseconds
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