| /external/clang/test/SemaTemplate/ |
| nested-name-spec-template.cpp | 5 template<typename T> struct Promote;
7 template<> struct Promote<short> {
11 template<> struct Promote<int> {
15 template<> struct Promote<float> {
19 Promote<short>::type *ret_intptr(int* ip) { return ip; }
20 Promote<int>::type *ret_intptr2(int* ip) { return ip; }
23 M::Promote<int>::type *ret_intptr3(int* ip) { return ip; }
24 M::template Promote<int>::type *ret_intptr4(int* ip) { return ip; } // expected-warning{{'template' keyword outside of a template}}
25 M::template Promote<int> pi; // expected-warning{{'template' keyword outside of a template}}
28 N::M::Promote<int>::type *ret_intptr5(int* ip) { return ip;
[all...] |
| /external/v8/test/mjsunit/regress/ |
| regress-sliced-external-cons-regexp.js | 11 gc(); // Promote cons.
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter7/ |
| toy.ml | 33 (* Promote allocas to registers. *)
|
| /art/runtime/jdwp/ |
| object_registry.h | 59 // also promote references to regular JNI global references (and demote them back again if
129 void Promote(ObjectRegistryEntry& entry)
|
| object_registry.cc | 200 Promote(*it->second);
222 void ObjectRegistry::Promote(ObjectRegistryEntry& entry) {
|
| /external/lldb/include/lldb/Core/ |
| Scalar.h | 19 // Operators are defined and Scalar objects will correctly promote
101 Promote(Scalar::Type type);
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 88 Promote, // This operation should be executed in a larger type.
207 // The default action for other vectors is to promote
422 /// legal (return 'Legal') or we need to promote it to a larger type (return
423 /// 'Promote'), or we need to expand it into multiple registers of smaller
434 /// to promote to. For integer types that are larger than the largest integer
556 getOperationAction(Op, VT) == Promote);
665 assert(Action != Promote && "Can't promote condition code!");
677 /// If the action for this operation is to promote, this method returns the
678 /// ValueType to promote to
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 489 // Promote the value if needed.
[all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 147 setOperationAction(ISD::STORE, MVT::f32, Promote);
150 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
153 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
156 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
159 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
162 setOperationAction(ISD::STORE, MVT::f64, Promote);
165 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
187 setOperationAction(ISD::LOAD, MVT::f32, Promote);
190 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
193 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
[all...] |
| SIISelLowering.cpp | 94 setOperationAction(ISD::SELECT, MVT::f64, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
139 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
144 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
174 setOperationAction(ISD::SELECT, MVT::i1, Promote);
[all...] |
| R600ISelLowering.cpp | 126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
134 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 284 // f16 is a storage-only type, always promote it to f32.
285 setOperationAction(ISD::SETCC, MVT::f16, Promote);
286 setOperationAction(ISD::BR_CC, MVT::f16, Promote);
287 setOperationAction(ISD::SELECT_CC, MVT::f16, Promote);
288 setOperationAction(ISD::SELECT, MVT::f16, Promote);
289 setOperationAction(ISD::FADD, MVT::f16, Promote);
290 setOperationAction(ISD::FSUB, MVT::f16, Promote);
291 setOperationAction(ISD::FMUL, MVT::f16, Promote);
292 setOperationAction(ISD::FDIV, MVT::f16, Promote);
293 setOperationAction(ISD::FREM, MVT::f16, Promote);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 113 SDValue Promote(SDValue Op);
336 case TargetLowering::Promote:
337 Result = Promote(Op);
366 SDValue VectorLegalizer::Promote(SDValue Op) {
372 // "Promote" the operation by extending the operand.
376 // Promote the operation by extending the operand.
387 "Can't promote a vector with multiple results!");
420 "Can't promote a vector with multiple results!");
422 // Normal getTypeToPromoteTo() doesn't work here, as that will promote
447 // For FP_TO_INT we promote the result type to a vector type with wide
[all...] |
| LegalizeDAG.cpp | 215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
738 case TargetLowering::Promote: {
741 "Can only promote stores to same size type")
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 153 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
154 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
155 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
315 // Promote the value if needed.
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 85 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
86 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
87 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
310 // Promote i8 to i16
610 // Promote the value if needed.
[all...] |
| /external/v8/test/mjsunit/harmony/ |
| private.js | 13 // contributors may be used to endorse or promote products derived
49 gc() // Promote existing symbols and then allocate some more.
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 157 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
177 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
179 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
180 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
181 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
184 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
195 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
197 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
198 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
203 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
[all...] |
| /external/lldb/source/Core/ |
| Scalar.cpp | 27 // Promote to max type currently follows the ANSI C rule for type
54 if (temp_value.Promote(lhs_type)) // Promote it
61 if (temp_value.Promote(rhs_type)) // Promote it
69 // Return the void type (zero) if we fail to promote either of the values.
345 Scalar::Promote(Scalar::Type type)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
133 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
[all...] |
| /external/v8/test/mjsunit/es6/ |
| symbols.js | 13 // contributors may be used to endorse or promote products derived
57 gc() // Promote existing symbols and then allocate some more.
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 210 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
215 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
229 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
230 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
231 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 219 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
220 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
221 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 219 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
220 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
262 // PTX does not directly support SELP of i1, so promote to i32 first
[all...] |
