| /external/llvm/lib/CodeGen/ |
| LiveDebugVariables.h | 43 /// renameRegister - Move any user variables in OldReg to NewReg:SubIdx.
46 /// @param SubIdx If NewReg is a virtual register, SubIdx may indicate a sub-
48 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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| ExpandPostRAPseudos.cpp | 89 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
90 unsigned SubIdx = MI->getOperand(3).getImm();
92 assert(SubIdx != 0 && "Invalid index for insert_subreg");
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
115 MI->RemoveOperand(3); // SubIdx
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| TargetRegisterInfo.cpp | 48 if (SubIdx) {
50 OS << ':' << TRI->getSubRegIndexName(SubIdx);
52 OS << ":sub(" << SubIdx << ')';
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| PeepholeOptimizer.cpp | 318 unsigned SrcReg, DstReg, SubIdx;
319 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
333 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
340 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
341 // SrcReg:SubIdx should be replaced.
343 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
368 // Only accept uses of SrcReg:SubIdx.
369 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
446 .addReg(DstReg, 0, SubIdx);
447 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set
[all...] |
| MachineCopyPropagation.cpp | 121 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def);
122 if (!SubIdx)
124 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
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| TargetInstrInfo.cpp | 286 unsigned SubIdx, unsigned &Size,
289 if (!SubIdx) {
295 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx);
301 int BitOffset = TRI->getSubRegIdxOffset(SubIdx);
319 unsigned SubIdx,
323 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
894 // Record Reg:SubReg, SubIdx.
[all...] |
| MachineInstr.cpp | 69 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
72 if (SubIdx && getSubReg())
73 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
75 if (SubIdx)
76 setSubReg(SubIdx);
[all...] |
| RegisterCoalescer.cpp | 207 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
375 "Cannot have a physical SubIdx");
[all...] |
| /external/llvm/lib/Target/R600/ |
| SIMachineFunctionInfo.cpp | 40 unsigned SubIdx) {
46 Offset += SubIdx * 4;
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| SIMachineFunctionInfo.h | 48 unsigned SubIdx);
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| SIRegisterInfo.h | 74 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
77 unsigned SubIdx) const;
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| SILoadStoreOptimizer.cpp | 74 unsigned SubIdx);
198 unsigned SubIdx) {
203 O.substVirtReg(DstReg, SubIdx, *TRI);
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| AMDGPUInstrInfo.h | 52 unsigned &DstReg, unsigned &SubIdx) const override;
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| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.h | 42 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
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| ThumbRegisterInfo.cpp | 65 unsigned SubIdx, int Val,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
85 unsigned SubIdx, int Val,
96 .addReg(DestReg, getDefRegState(true), SubIdx)
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred,
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
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| ARMBaseRegisterInfo.h | 162 DebugLoc dl, unsigned DestReg, unsigned SubIdx,
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| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 345 const char *getSubRegIndexName(unsigned SubIdx) const {
346 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
348 return SubRegIndexNames[SubIdx-1];
352 /// register that are covered by SubIdx.
370 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
371 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
372 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
373 return SubRegIndexLaneMasks[SubIdx];
471 /// Reg so its sub-register of index SubIdx is Reg
[all...] |
| TargetInstrInfo.h | 123 /// SubIdx.
126 unsigned &SubIdx) const {
208 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
224 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
225 /// SubIdx.
228 unsigned DestReg, unsigned SubIdx,
285 unsigned SubIdx;
287 unsigned SubIdx = 0)
288 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {}
[all...] |
| /external/llvm/lib/MC/ |
| MCRegisterInfo.cpp | 18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
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| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.h | 347 // registers have a SubIdx sub-register.
349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
350 return SubClassWithSubReg.lookup(SubIdx);
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx,
355 SubClassWithSubReg[SubIdx] = SubRC;
359 // containing only SubIdx super-registers of this class.
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx,
366 SuperRegClasses[SubIdx].insert(SuperRC);
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| CodeGenRegisters.cpp | 469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second);
470 if (!SubIdx)
473 NewIdx->addComposite(SI->first, SubIdx);
495 // Topological signature computed from SubIdx, TopoId(SubReg).
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 440 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
443 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
445 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
450 // VReg has been adjusted. It can be used with SubIdx operands now.
456 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
457 assert(RC && "No legal register class for VT supports that SubIdx");
489 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
498 SubIdx == DefSubIdx &&
510 // VReg may not support a SubIdx sub-register, and we may need to
513 VReg = ConstrainForSubReg(VReg, SubIdx,
[all...] |
| InstrEmitter.h | 84 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
86 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 158 unsigned &SubIdx) const {
165 SubIdx = PPC::sub_32;
661 unsigned SubIdx;
665 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break;
666 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break;
667 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break;
668 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break;
669 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break;
670 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break;
671 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.cpp | 38 unsigned &SubIdx) const {
|
