1 //===-- AArch64A57FPLoadBalancing.cpp - Balance FP ops statically on A57---===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // For best-case performance on Cortex-A57, we should try to use a balanced 10 // mix of odd and even D-registers when performing a critical sequence of 11 // independent, non-quadword FP/ASIMD floating-point multiply or 12 // multiply-accumulate operations. 13 // 14 // This pass attempts to detect situations where the register allocation may 15 // adversely affect this load balancing and to change the registers used so as 16 // to better utilize the CPU. 17 // 18 // Ideally we'd just take each multiply or multiply-accumulate in turn and 19 // allocate it alternating even or odd registers. However, multiply-accumulates 20 // are most efficiently performed in the same functional unit as their 21 // accumulation operand. Therefore this pass tries to find maximal sequences 22 // ("Chains") of multiply-accumulates linked via their accumulation operand, 23 // and assign them all the same "color" (oddness/evenness). 24 // 25 // This optimization affects S-register and D-register floating point 26 // multiplies and FMADD/FMAs, as well as vector (floating point only) muls and 27 // FMADD/FMA. Q register instructions (and 128-bit vector instructions) are 28 // not affected. 29 //===----------------------------------------------------------------------===// 30 31 #include "AArch64.h" 32 #include "AArch64InstrInfo.h" 33 #include "AArch64Subtarget.h" 34 #include "llvm/ADT/BitVector.h" 35 #include "llvm/ADT/EquivalenceClasses.h" 36 #include "llvm/CodeGen/MachineFunction.h" 37 #include "llvm/CodeGen/MachineFunctionPass.h" 38 #include "llvm/CodeGen/MachineInstr.h" 39 #include "llvm/CodeGen/MachineInstrBuilder.h" 40 #include "llvm/CodeGen/MachineRegisterInfo.h" 41 #include "llvm/CodeGen/RegisterClassInfo.h" 42 #include "llvm/CodeGen/RegisterScavenging.h" 43 #include "llvm/Support/CommandLine.h" 44 #include "llvm/Support/Debug.h" 45 #include "llvm/Support/raw_ostream.h" 46 #include <list> 47 using namespace llvm; 48 49 #define DEBUG_TYPE "aarch64-a57-fp-load-balancing" 50 51 // Enforce the algorithm to use the scavenged register even when the original 52 // destination register is the correct color. Used for testing. 53 static cl::opt<bool> 54 TransformAll("aarch64-a57-fp-load-balancing-force-all", 55 cl::desc("Always modify dest registers regardless of color"), 56 cl::init(false), cl::Hidden); 57 58 // Never use the balance information obtained from chains - return a specific 59 // color always. Used for testing. 60 static cl::opt<unsigned> 61 OverrideBalance("aarch64-a57-fp-load-balancing-override", 62 cl::desc("Ignore balance information, always return " 63 "(1: Even, 2: Odd)."), 64 cl::init(0), cl::Hidden); 65 66 //===----------------------------------------------------------------------===// 67 // Helper functions 68 69 // Is the instruction a type of multiply on 64-bit (or 32-bit) FPRs? 70 static bool isMul(MachineInstr *MI) { 71 switch (MI->getOpcode()) { 72 case AArch64::FMULSrr: 73 case AArch64::FNMULSrr: 74 case AArch64::FMULDrr: 75 case AArch64::FNMULDrr: 76 return true; 77 default: 78 return false; 79 } 80 } 81 82 // Is the instruction a type of FP multiply-accumulate on 64-bit (or 32-bit) FPRs? 83 static bool isMla(MachineInstr *MI) { 84 switch (MI->getOpcode()) { 85 case AArch64::FMSUBSrrr: 86 case AArch64::FMADDSrrr: 87 case AArch64::FNMSUBSrrr: 88 case AArch64::FNMADDSrrr: 89 case AArch64::FMSUBDrrr: 90 case AArch64::FMADDDrrr: 91 case AArch64::FNMSUBDrrr: 92 case AArch64::FNMADDDrrr: 93 return true; 94 default: 95 return false; 96 } 97 } 98 99 namespace llvm { 100 static void initializeAArch64A57FPLoadBalancingPass(PassRegistry &); 101 } 102 103 //===----------------------------------------------------------------------===// 104 105 namespace { 106 /// A "color", which is either even or odd. Yes, these aren't really colors 107 /// but the algorithm is conceptually doing two-color graph coloring. 108 enum class Color { Even, Odd }; 109 #ifndef NDEBUG 110 static const char *ColorNames[2] = { "Even", "Odd" }; 111 #endif 112 113 class Chain; 114 115 class AArch64A57FPLoadBalancing : public MachineFunctionPass { 116 MachineRegisterInfo *MRI; 117 const TargetRegisterInfo *TRI; 118 RegisterClassInfo RCI; 119 120 public: 121 static char ID; 122 explicit AArch64A57FPLoadBalancing() : MachineFunctionPass(ID) { 123 initializeAArch64A57FPLoadBalancingPass(*PassRegistry::getPassRegistry()); 124 } 125 126 bool runOnMachineFunction(MachineFunction &F) override; 127 128 const char *getPassName() const override { 129 return "A57 FP Anti-dependency breaker"; 130 } 131 132 void getAnalysisUsage(AnalysisUsage &AU) const override { 133 AU.setPreservesCFG(); 134 MachineFunctionPass::getAnalysisUsage(AU); 135 } 136 137 private: 138 bool runOnBasicBlock(MachineBasicBlock &MBB); 139 bool colorChainSet(std::vector<Chain*> GV, MachineBasicBlock &MBB, 140 int &Balance); 141 bool colorChain(Chain *G, Color C, MachineBasicBlock &MBB); 142 int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB); 143 void scanInstruction(MachineInstr *MI, unsigned Idx, 144 std::map<unsigned, Chain*> &Active, 145 std::vector<std::unique_ptr<Chain>> &AllChains); 146 void maybeKillChain(MachineOperand &MO, unsigned Idx, 147 std::map<unsigned, Chain*> &RegChains); 148 Color getColor(unsigned Register); 149 Chain *getAndEraseNext(Color PreferredColor, std::vector<Chain*> &L); 150 }; 151 } 152 153 char AArch64A57FPLoadBalancing::ID = 0; 154 155 INITIALIZE_PASS_BEGIN(AArch64A57FPLoadBalancing, DEBUG_TYPE, 156 "AArch64 A57 FP Load-Balancing", false, false) 157 INITIALIZE_PASS_END(AArch64A57FPLoadBalancing, DEBUG_TYPE, 158 "AArch64 A57 FP Load-Balancing", false, false) 159 160 namespace { 161 /// A Chain is a sequence of instructions that are linked together by 162 /// an accumulation operand. For example: 163 /// 164 /// fmul d0<def>, ? 165 /// fmla d1<def>, ?, ?, d0<kill> 166 /// fmla d2<def>, ?, ?, d1<kill> 167 /// 168 /// There may be other instructions interleaved in the sequence that 169 /// do not belong to the chain. These other instructions must not use 170 /// the "chain" register at any point. 171 /// 172 /// We currently only support chains where the "chain" operand is killed 173 /// at each link in the chain for simplicity. 174 /// A chain has three important instructions - Start, Last and Kill. 175 /// * The start instruction is the first instruction in the chain. 176 /// * Last is the final instruction in the chain. 177 /// * Kill may or may not be defined. If defined, Kill is the instruction 178 /// where the outgoing value of the Last instruction is killed. 179 /// This information is important as if we know the outgoing value is 180 /// killed with no intervening uses, we can safely change its register. 181 /// 182 /// Without a kill instruction, we must assume the outgoing value escapes 183 /// beyond our model and either must not change its register or must 184 /// create a fixup FMOV to keep the old register value consistent. 185 /// 186 class Chain { 187 public: 188 /// The important (marker) instructions. 189 MachineInstr *StartInst, *LastInst, *KillInst; 190 /// The index, from the start of the basic block, that each marker 191 /// appears. These are stored so we can do quick interval tests. 192 unsigned StartInstIdx, LastInstIdx, KillInstIdx; 193 /// All instructions in the chain. 194 std::set<MachineInstr*> Insts; 195 /// True if KillInst cannot be modified. If this is true, 196 /// we cannot change LastInst's outgoing register. 197 /// This will be true for tied values and regmasks. 198 bool KillIsImmutable; 199 /// The "color" of LastInst. This will be the preferred chain color, 200 /// as changing intermediate nodes is easy but changing the last 201 /// instruction can be more tricky. 202 Color LastColor; 203 204 Chain(MachineInstr *MI, unsigned Idx, Color C) 205 : StartInst(MI), LastInst(MI), KillInst(nullptr), 206 StartInstIdx(Idx), LastInstIdx(Idx), KillInstIdx(0), 207 LastColor(C) { 208 Insts.insert(MI); 209 } 210 211 /// Add a new instruction into the chain. The instruction's dest operand 212 /// has the given color. 213 void add(MachineInstr *MI, unsigned Idx, Color C) { 214 LastInst = MI; 215 LastInstIdx = Idx; 216 LastColor = C; 217 assert((KillInstIdx == 0 || LastInstIdx < KillInstIdx) && 218 "Chain: broken invariant. A Chain can only be killed after its last " 219 "def"); 220 221 Insts.insert(MI); 222 } 223 224 /// Return true if MI is a member of the chain. 225 bool contains(MachineInstr *MI) { return Insts.count(MI) > 0; } 226 227 /// Return the number of instructions in the chain. 228 unsigned size() const { 229 return Insts.size(); 230 } 231 232 /// Inform the chain that its last active register (the dest register of 233 /// LastInst) is killed by MI with no intervening uses or defs. 234 void setKill(MachineInstr *MI, unsigned Idx, bool Immutable) { 235 KillInst = MI; 236 KillInstIdx = Idx; 237 KillIsImmutable = Immutable; 238 assert((KillInstIdx == 0 || LastInstIdx < KillInstIdx) && 239 "Chain: broken invariant. A Chain can only be killed after its last " 240 "def"); 241 } 242 243 /// Return the first instruction in the chain. 244 MachineInstr *getStart() const { return StartInst; } 245 /// Return the last instruction in the chain. 246 MachineInstr *getLast() const { return LastInst; } 247 /// Return the "kill" instruction (as set with setKill()) or NULL. 248 MachineInstr *getKill() const { return KillInst; } 249 /// Return an instruction that can be used as an iterator for the end 250 /// of the chain. This is the maximum of KillInst (if set) and LastInst. 251 MachineBasicBlock::iterator getEnd() const { 252 return ++MachineBasicBlock::iterator(KillInst ? KillInst : LastInst); 253 } 254 255 /// Can the Kill instruction (assuming one exists) be modified? 256 bool isKillImmutable() const { return KillIsImmutable; } 257 258 /// Return the preferred color of this chain. 259 Color getPreferredColor() { 260 if (OverrideBalance != 0) 261 return OverrideBalance == 1 ? Color::Even : Color::Odd; 262 return LastColor; 263 } 264 265 /// Return true if this chain (StartInst..KillInst) overlaps with Other. 266 bool rangeOverlapsWith(const Chain &Other) const { 267 unsigned End = KillInst ? KillInstIdx : LastInstIdx; 268 unsigned OtherEnd = Other.KillInst ? 269 Other.KillInstIdx : Other.LastInstIdx; 270 271 return StartInstIdx <= OtherEnd && Other.StartInstIdx <= End; 272 } 273 274 /// Return true if this chain starts before Other. 275 bool startsBefore(const Chain *Other) const { 276 return StartInstIdx < Other->StartInstIdx; 277 } 278 279 /// Return true if the group will require a fixup MOV at the end. 280 bool requiresFixup() const { 281 return (getKill() && isKillImmutable()) || !getKill(); 282 } 283 284 /// Return a simple string representation of the chain. 285 std::string str() const { 286 std::string S; 287 raw_string_ostream OS(S); 288 289 OS << "{"; 290 StartInst->print(OS, /* SkipOpers= */true); 291 OS << " -> "; 292 LastInst->print(OS, /* SkipOpers= */true); 293 if (KillInst) { 294 OS << " (kill @ "; 295 KillInst->print(OS, /* SkipOpers= */true); 296 OS << ")"; 297 } 298 OS << "}"; 299 300 return OS.str(); 301 } 302 303 }; 304 305 } // end anonymous namespace 306 307 //===----------------------------------------------------------------------===// 308 309 bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) { 310 // Don't do anything if this isn't an A53 or A57. 311 if (!(F.getSubtarget<AArch64Subtarget>().isCortexA53() || 312 F.getSubtarget<AArch64Subtarget>().isCortexA57())) 313 return false; 314 315 bool Changed = false; 316 DEBUG(dbgs() << "***** AArch64A57FPLoadBalancing *****\n"); 317 318 MRI = &F.getRegInfo(); 319 TRI = F.getRegInfo().getTargetRegisterInfo(); 320 RCI.runOnMachineFunction(F); 321 322 for (auto &MBB : F) { 323 Changed |= runOnBasicBlock(MBB); 324 } 325 326 return Changed; 327 } 328 329 bool AArch64A57FPLoadBalancing::runOnBasicBlock(MachineBasicBlock &MBB) { 330 bool Changed = false; 331 DEBUG(dbgs() << "Running on MBB: " << MBB << " - scanning instructions...\n"); 332 333 // First, scan the basic block producing a set of chains. 334 335 // The currently "active" chains - chains that can be added to and haven't 336 // been killed yet. This is keyed by register - all chains can only have one 337 // "link" register between each inst in the chain. 338 std::map<unsigned, Chain*> ActiveChains; 339 std::vector<std::unique_ptr<Chain>> AllChains; 340 unsigned Idx = 0; 341 for (auto &MI : MBB) 342 scanInstruction(&MI, Idx++, ActiveChains, AllChains); 343 344 DEBUG(dbgs() << "Scan complete, "<< AllChains.size() << " chains created.\n"); 345 346 // Group the chains into disjoint sets based on their liveness range. This is 347 // a poor-man's version of graph coloring. Ideally we'd create an interference 348 // graph and perform full-on graph coloring on that, but; 349 // (a) That's rather heavyweight for only two colors. 350 // (b) We expect multiple disjoint interference regions - in practice the live 351 // range of chains is quite small and they are clustered between loads 352 // and stores. 353 EquivalenceClasses<Chain*> EC; 354 for (auto &I : AllChains) 355 EC.insert(I.get()); 356 357 for (auto &I : AllChains) 358 for (auto &J : AllChains) 359 if (I != J && I->rangeOverlapsWith(*J)) 360 EC.unionSets(I.get(), J.get()); 361 DEBUG(dbgs() << "Created " << EC.getNumClasses() << " disjoint sets.\n"); 362 363 // Now we assume that every member of an equivalence class interferes 364 // with every other member of that class, and with no members of other classes. 365 366 // Convert the EquivalenceClasses to a simpler set of sets. 367 std::vector<std::vector<Chain*> > V; 368 for (auto I = EC.begin(), E = EC.end(); I != E; ++I) { 369 std::vector<Chain*> Cs(EC.member_begin(I), EC.member_end()); 370 if (Cs.empty()) continue; 371 V.push_back(std::move(Cs)); 372 } 373 374 // Now we have a set of sets, order them by start address so 375 // we can iterate over them sequentially. 376 std::sort(V.begin(), V.end(), 377 [](const std::vector<Chain*> &A, 378 const std::vector<Chain*> &B) { 379 return A.front()->startsBefore(B.front()); 380 }); 381 382 // As we only have two colors, we can track the global (BB-level) balance of 383 // odds versus evens. We aim to keep this near zero to keep both execution 384 // units fed. 385 // Positive means we're even-heavy, negative we're odd-heavy. 386 // 387 // FIXME: If chains have interdependencies, for example: 388 // mul r0, r1, r2 389 // mul r3, r0, r1 390 // We do not model this and may color each one differently, assuming we'll 391 // get ILP when we obviously can't. This hasn't been seen to be a problem 392 // in practice so far, so we simplify the algorithm by ignoring it. 393 int Parity = 0; 394 395 for (auto &I : V) 396 Changed |= colorChainSet(std::move(I), MBB, Parity); 397 398 return Changed; 399 } 400 401 Chain *AArch64A57FPLoadBalancing::getAndEraseNext(Color PreferredColor, 402 std::vector<Chain*> &L) { 403 if (L.empty()) 404 return nullptr; 405 406 // We try and get the best candidate from L to color next, given that our 407 // preferred color is "PreferredColor". L is ordered from larger to smaller 408 // chains. It is beneficial to color the large chains before the small chains, 409 // but if we can't find a chain of the maximum length with the preferred color, 410 // we fuzz the size and look for slightly smaller chains before giving up and 411 // returning a chain that must be recolored. 412 413 // FIXME: Does this need to be configurable? 414 const unsigned SizeFuzz = 1; 415 unsigned MinSize = L.front()->size() - SizeFuzz; 416 for (auto I = L.begin(), E = L.end(); I != E; ++I) { 417 if ((*I)->size() <= MinSize) { 418 // We've gone past the size limit. Return the previous item. 419 Chain *Ch = *--I; 420 L.erase(I); 421 return Ch; 422 } 423 424 if ((*I)->getPreferredColor() == PreferredColor) { 425 Chain *Ch = *I; 426 L.erase(I); 427 return Ch; 428 } 429 } 430 431 // Bailout case - just return the first item. 432 Chain *Ch = L.front(); 433 L.erase(L.begin()); 434 return Ch; 435 } 436 437 bool AArch64A57FPLoadBalancing::colorChainSet(std::vector<Chain*> GV, 438 MachineBasicBlock &MBB, 439 int &Parity) { 440 bool Changed = false; 441 DEBUG(dbgs() << "colorChainSet(): #sets=" << GV.size() << "\n"); 442 443 // Sort by descending size order so that we allocate the most important 444 // sets first. 445 // Tie-break equivalent sizes by sorting chains requiring fixups before 446 // those without fixups. The logic here is that we should look at the 447 // chains that we cannot change before we look at those we can, 448 // so the parity counter is updated and we know what color we should 449 // change them to! 450 // Final tie-break with instruction order so pass output is stable (i.e. not 451 // dependent on malloc'd pointer values). 452 std::sort(GV.begin(), GV.end(), [](const Chain *G1, const Chain *G2) { 453 if (G1->size() != G2->size()) 454 return G1->size() > G2->size(); 455 if (G1->requiresFixup() != G2->requiresFixup()) 456 return G1->requiresFixup() > G2->requiresFixup(); 457 // Make sure startsBefore() produces a stable final order. 458 assert((G1 == G2 || (G1->startsBefore(G2) ^ G2->startsBefore(G1))) && 459 "Starts before not total order!"); 460 return G1->startsBefore(G2); 461 }); 462 463 Color PreferredColor = Parity < 0 ? Color::Even : Color::Odd; 464 while (Chain *G = getAndEraseNext(PreferredColor, GV)) { 465 // Start off by assuming we'll color to our own preferred color. 466 Color C = PreferredColor; 467 if (Parity == 0) 468 // But if we really don't care, use the chain's preferred color. 469 C = G->getPreferredColor(); 470 471 DEBUG(dbgs() << " - Parity=" << Parity << ", Color=" 472 << ColorNames[(int)C] << "\n"); 473 474 // If we'll need a fixup FMOV, don't bother. Testing has shown that this 475 // happens infrequently and when it does it has at least a 50% chance of 476 // slowing code down instead of speeding it up. 477 if (G->requiresFixup() && C != G->getPreferredColor()) { 478 C = G->getPreferredColor(); 479 DEBUG(dbgs() << " - " << G->str() << " - not worthwhile changing; " 480 "color remains " << ColorNames[(int)C] << "\n"); 481 } 482 483 Changed |= colorChain(G, C, MBB); 484 485 Parity += (C == Color::Even) ? G->size() : -G->size(); 486 PreferredColor = Parity < 0 ? Color::Even : Color::Odd; 487 } 488 489 return Changed; 490 } 491 492 int AArch64A57FPLoadBalancing::scavengeRegister(Chain *G, Color C, 493 MachineBasicBlock &MBB) { 494 RegScavenger RS; 495 RS.enterBasicBlock(&MBB); 496 RS.forward(MachineBasicBlock::iterator(G->getStart())); 497 498 // Can we find an appropriate register that is available throughout the life 499 // of the chain? 500 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass; 501 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID)); 502 for (MachineBasicBlock::iterator I = G->getStart(), E = G->getEnd(); 503 I != E; ++I) { 504 RS.forward(I); 505 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID)); 506 507 // Remove any registers clobbered by a regmask or any def register that is 508 // immediately dead. 509 for (auto J : I->operands()) { 510 if (J.isRegMask()) 511 AvailableRegs.clearBitsNotInMask(J.getRegMask()); 512 513 if (J.isReg() && J.isDef() && AvailableRegs[J.getReg()]) { 514 assert(J.isDead() && "Non-dead def should have been removed by now!"); 515 AvailableRegs.reset(J.getReg()); 516 } 517 } 518 } 519 520 // Make sure we allocate in-order, to get the cheapest registers first. 521 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); 522 for (auto Reg : Ord) { 523 if (!AvailableRegs[Reg]) 524 continue; 525 if ((C == Color::Even && (Reg % 2) == 0) || 526 (C == Color::Odd && (Reg % 2) == 1)) 527 return Reg; 528 } 529 530 return -1; 531 } 532 533 bool AArch64A57FPLoadBalancing::colorChain(Chain *G, Color C, 534 MachineBasicBlock &MBB) { 535 bool Changed = false; 536 DEBUG(dbgs() << " - colorChain(" << G->str() << ", " 537 << ColorNames[(int)C] << ")\n"); 538 539 // Try and obtain a free register of the right class. Without a register 540 // to play with we cannot continue. 541 int Reg = scavengeRegister(G, C, MBB); 542 if (Reg == -1) { 543 DEBUG(dbgs() << "Scavenging (thus coloring) failed!\n"); 544 return false; 545 } 546 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n"); 547 548 std::map<unsigned, unsigned> Substs; 549 for (MachineBasicBlock::iterator I = G->getStart(), E = G->getEnd(); 550 I != E; ++I) { 551 if (!G->contains(I) && 552 (&*I != G->getKill() || G->isKillImmutable())) 553 continue; 554 555 // I is a member of G, or I is a mutable instruction that kills G. 556 557 std::vector<unsigned> ToErase; 558 for (auto &U : I->operands()) { 559 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) { 560 unsigned OrigReg = U.getReg(); 561 U.setReg(Substs[OrigReg]); 562 if (U.isKill()) 563 // Don't erase straight away, because there may be other operands 564 // that also reference this substitution! 565 ToErase.push_back(OrigReg); 566 } else if (U.isRegMask()) { 567 for (auto J : Substs) { 568 if (U.clobbersPhysReg(J.first)) 569 ToErase.push_back(J.first); 570 } 571 } 572 } 573 // Now it's safe to remove the substs identified earlier. 574 for (auto J : ToErase) 575 Substs.erase(J); 576 577 // Only change the def if this isn't the last instruction. 578 if (&*I != G->getKill()) { 579 MachineOperand &MO = I->getOperand(0); 580 581 bool Change = TransformAll || getColor(MO.getReg()) != C; 582 if (G->requiresFixup() && &*I == G->getLast()) 583 Change = false; 584 585 if (Change) { 586 Substs[MO.getReg()] = Reg; 587 MO.setReg(Reg); 588 MRI->setPhysRegUsed(Reg); 589 590 Changed = true; 591 } 592 } 593 } 594 assert(Substs.size() == 0 && "No substitutions should be left active!"); 595 596 if (G->getKill()) { 597 DEBUG(dbgs() << " - Kill instruction seen.\n"); 598 } else { 599 // We didn't have a kill instruction, but we didn't seem to need to change 600 // the destination register anyway. 601 DEBUG(dbgs() << " - Destination register not changed.\n"); 602 } 603 return Changed; 604 } 605 606 void AArch64A57FPLoadBalancing::scanInstruction( 607 MachineInstr *MI, unsigned Idx, std::map<unsigned, Chain *> &ActiveChains, 608 std::vector<std::unique_ptr<Chain>> &AllChains) { 609 // Inspect "MI", updating ActiveChains and AllChains. 610 611 if (isMul(MI)) { 612 613 for (auto &I : MI->uses()) 614 maybeKillChain(I, Idx, ActiveChains); 615 for (auto &I : MI->defs()) 616 maybeKillChain(I, Idx, ActiveChains); 617 618 // Create a new chain. Multiplies don't require forwarding so can go on any 619 // unit. 620 unsigned DestReg = MI->getOperand(0).getReg(); 621 622 DEBUG(dbgs() << "New chain started for register " 623 << TRI->getName(DestReg) << " at " << *MI); 624 625 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); 626 ActiveChains[DestReg] = G.get(); 627 AllChains.push_back(std::move(G)); 628 629 } else if (isMla(MI)) { 630 631 // It is beneficial to keep MLAs on the same functional unit as their 632 // accumulator operand. 633 unsigned DestReg = MI->getOperand(0).getReg(); 634 unsigned AccumReg = MI->getOperand(3).getReg(); 635 636 maybeKillChain(MI->getOperand(1), Idx, ActiveChains); 637 maybeKillChain(MI->getOperand(2), Idx, ActiveChains); 638 if (DestReg != AccumReg) 639 maybeKillChain(MI->getOperand(0), Idx, ActiveChains); 640 641 if (ActiveChains.find(AccumReg) != ActiveChains.end()) { 642 DEBUG(dbgs() << "Chain found for accumulator register " 643 << TRI->getName(AccumReg) << " in MI " << *MI); 644 645 // For simplicity we only chain together sequences of MULs/MLAs where the 646 // accumulator register is killed on each instruction. This means we don't 647 // need to track other uses of the registers we want to rewrite. 648 // 649 // FIXME: We could extend to handle the non-kill cases for more coverage. 650 if (MI->getOperand(3).isKill()) { 651 // Add to chain. 652 DEBUG(dbgs() << "Instruction was successfully added to chain.\n"); 653 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); 654 // Handle cases where the destination is not the same as the accumulator. 655 if (DestReg != AccumReg) { 656 ActiveChains[DestReg] = ActiveChains[AccumReg]; 657 ActiveChains.erase(AccumReg); 658 } 659 return; 660 } 661 662 DEBUG(dbgs() << "Cannot add to chain because accumulator operand wasn't " 663 << "marked <kill>!\n"); 664 maybeKillChain(MI->getOperand(3), Idx, ActiveChains); 665 } 666 667 DEBUG(dbgs() << "Creating new chain for dest register " 668 << TRI->getName(DestReg) << "\n"); 669 auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg)); 670 ActiveChains[DestReg] = G.get(); 671 AllChains.push_back(std::move(G)); 672 673 } else { 674 675 // Non-MUL or MLA instruction. Invalidate any chain in the uses or defs 676 // lists. 677 for (auto &I : MI->uses()) 678 maybeKillChain(I, Idx, ActiveChains); 679 for (auto &I : MI->defs()) 680 maybeKillChain(I, Idx, ActiveChains); 681 682 } 683 } 684 685 void AArch64A57FPLoadBalancing:: 686 maybeKillChain(MachineOperand &MO, unsigned Idx, 687 std::map<unsigned, Chain*> &ActiveChains) { 688 // Given an operand and the set of active chains (keyed by register), 689 // determine if a chain should be ended and remove from ActiveChains. 690 MachineInstr *MI = MO.getParent(); 691 692 if (MO.isReg()) { 693 694 // If this is a KILL of a current chain, record it. 695 if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) { 696 DEBUG(dbgs() << "Kill seen for chain " << TRI->getName(MO.getReg()) 697 << "\n"); 698 ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied()); 699 } 700 ActiveChains.erase(MO.getReg()); 701 702 } else if (MO.isRegMask()) { 703 704 for (auto I = ActiveChains.begin(), E = ActiveChains.end(); 705 I != E;) { 706 if (MO.clobbersPhysReg(I->first)) { 707 DEBUG(dbgs() << "Kill (regmask) seen for chain " 708 << TRI->getName(I->first) << "\n"); 709 I->second->setKill(MI, Idx, /*Immutable=*/true); 710 ActiveChains.erase(I++); 711 } else 712 ++I; 713 } 714 715 } 716 } 717 718 Color AArch64A57FPLoadBalancing::getColor(unsigned Reg) { 719 if ((TRI->getEncodingValue(Reg) % 2) == 0) 720 return Color::Even; 721 else 722 return Color::Odd; 723 } 724 725 // Factory function used by AArch64TargetMachine to add the pass to the passmanager. 726 FunctionPass *llvm::createAArch64A57FPLoadBalancing() { 727 return new AArch64A57FPLoadBalancing(); 728 } 729