/art/compiler/dex/quick/mips/ |
call_mips.cc | 124 const RegStorage rs_ra = TargetPtrReg(kLr); 205 const RegStorage rs_ra = TargetPtrReg(kLr); 219 LoadRefDisp(TargetPtrReg(kSelf), ex_offset, rl_result.reg, kNotVolatile); 221 StoreRefDisp(TargetPtrReg(kSelf), ex_offset, reset_reg, kNotVolatile); 231 LoadWordDisp(TargetPtrReg(kSelf), Thread::CardTableOffset<8>().Int32Value(), reg_card_base); 236 LoadWordDisp(TargetPtrReg(kSelf), Thread::CardTableOffset<4>().Int32Value(), reg_card_base); 288 const RegStorage rs_sp = TargetPtrReg(kSp); 298 LoadWordDisp(TargetPtrReg(kSelf), Thread::StackEndOffset<8>().Int32Value(), check_reg); 300 Load32Disp(TargetPtrReg(kSelf), Thread::StackEndOffset<4>().Int32Value(), check_reg); 326 m2l_->LoadWordDisp(m2l_->TargetPtrReg(kSp), 0, m2l_->TargetPtrReg(kLr)) [all...] |
target_mips.cc | 767 LoadWordDisp(TargetPtrReg(kSelf), GetThreadOffset<8>(trampoline).Int32Value(), 768 TargetPtrReg(kInvokeTgt)); 770 LoadWordDisp(TargetPtrReg(kSelf), GetThreadOffset<4>(trampoline).Int32Value(), 771 TargetPtrReg(kInvokeTgt)); 773 return TargetPtrReg(kInvokeTgt); 780 LoadWordDisp(TargetPtrReg(kSelf), Thread::ThreadSuspendTriggerOffset<8>().Int32Value(), tmp); 782 LoadWordDisp(TargetPtrReg(kSelf), Thread::ThreadSuspendTriggerOffset<4>().Int32Value(), tmp); 851 const RegStorage rs_sp = TargetPtrReg(kSp); 871 const RegStorage rs_sp = TargetPtrReg(kSp); [all...] |
utility_mips.cc | 771 DCHECK_EQ(r_base, TargetPtrReg(kSp)); 824 DCHECK_EQ(r_base, TargetPtrReg(kSp)); 942 DCHECK_EQ(r_base, TargetPtrReg(kSp)); 992 DCHECK_EQ(r_base, TargetPtrReg(kSp)); [all...] |
codegen_mips.h | 105 RegStorage TargetPtrReg(SpecialTargetRegister reg) OVERRIDE {
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int_mips.cc | 455 OpRegImm(kOpSub, TargetPtrReg(kSuspend), 1); 456 return OpCmpImmBranch((target == nullptr) ? kCondEq : kCondNe, TargetPtrReg(kSuspend), 0, target);
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/art/compiler/dex/quick/ |
gen_loadstore.cc | 64 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, op_size, kNotVolatile); 94 LoadBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_src.s_reg_low), r_dest, k64, kNotVolatile); 180 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, kNotVolatile); 182 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg); 271 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile); 299 Store32Disp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg); 335 StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(rl_dest.s_reg_low), rl_dest.reg, k64, kNotVolatile);
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gen_invoke.cc | 418 StoreBaseDisp(TargetPtrReg(kSp), 0, rl_src.reg, kWord, kNotVolatile); 469 StoreRefDisp(TargetPtrReg(kSp), offset, reg, kNotVolatile); 471 StoreBaseDisp(TargetPtrReg(kSp), offset, reg, t_loc->wide ? k64 : k32, kNotVolatile); 479 LoadRefDisp(TargetPtrReg(kSp), offset, t_loc->reg, kNotVolatile); 481 LoadBaseDisp(TargetPtrReg(kSp), offset, t_loc->reg, t_loc->wide ? k64 : k32, 510 cg->TargetPtrReg(kInvokeTgt)); 548 cg->LoadWordDisp(cg->TargetPtrReg(kArg0), offset, cg->TargetPtrReg(kArg0)); 595 cg->LoadWordDisp(cg->TargetPtrReg(kArg0), offset, cg->TargetPtrReg(kArg0)) [all...] |
mir_to_lir.cc | 141 StoreBaseDisp(TargetPtrReg(kSp), offset, reg_arg, k32, kNotVolatile); 147 LoadBaseDisp(TargetPtrReg(kSp), offset, reg_arg, wide ? k64 : k32, kNotVolatile); 191 StoreBaseDisp(TargetPtrReg(kSp), offset, reg_arg, k32, kNotVolatile); 197 LoadBaseDisp(TargetPtrReg(kSp), offset, rl_dest.reg, op_size, kNotVolatile); 215 StoreBaseDisp(TargetPtrReg(kSp), offset, reg_arg, size, kNotVolatile); 227 LoadBaseDisp(TargetPtrReg(kSp), offset, reg_arg, size, kNotVolatile); [all...] |
ralloc_util.cc | 746 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); 754 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, k64, kNotVolatile); 766 StoreBaseDisp(TargetPtrReg(kSp), VRegOffset(v_reg), reg, kWord, kNotVolatile); [all...] |
gen_common.cc | 569 StoreRefDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, kNotVolatile); 571 Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 603 OpRegRegImm(kOpAdd, r_src, TargetPtrReg(kSp), SRegOffset(rl_first.s_reg_low)); [all...] |
codegen_util.cc | [all...] |
mir_to_lir.h | [all...] |
/art/compiler/dex/quick/arm64/ |
call_arm64.cc | 475 kArm64PointerSize).Int32Value(), cg->TargetPtrReg(kInvokeTgt)); 485 cg->LoadConstantWide(cg->TargetPtrReg(kInvokeTgt), direct_code); 502 RegStorage arg0_ref = cg->TargetPtrReg(kArg0); 522 cg->LoadConstantWide(cg->TargetPtrReg(kInvokeTgt), direct_code); 551 kArm64PointerSize).Int32Value(), cg->TargetPtrReg(kInvokeTgt)); 588 call_insn = OpReg(kOpBlx, TargetPtrReg(kInvokeTgt));
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codegen_arm64.h | 97 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE {
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/art/compiler/dex/quick/arm/ |
call_arm.cc | 641 kArmPointerSize).Int32Value(), cg->TargetPtrReg(kInvokeTgt)); 651 cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); 688 cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code); 719 kArmPointerSize).Int32Value(), cg->TargetPtrReg(kInvokeTgt)); 756 call_insn = OpReg(kOpBlx, TargetPtrReg(kInvokeTgt));
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/art/compiler/dex/quick/x86/ |
target_x86.cc | [all...] |
codegen_x86.h | 136 RegStorage TargetPtrReg(SpecialTargetRegister symbolic_reg) OVERRIDE { [all...] |