| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 98 CGI.TheDef->getName() + "'!");
137 + CGI.TheDef->getName() + "'");
144 + CGI.TheDef->getName() + "'");
152 PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'");
157 + CGI.TheDef->getName() + "'");
161 PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() +
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| CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic.
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| InstrInfoEmitter.cpp | 209 if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable"))
221 OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName());
363 Record *Inst = II->TheDef;
391 InstrNames.add(Inst->TheDef->getName());
409 OS << InstrNames.get(Inst->TheDef->getName()) << "U, ";
479 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
515 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
523 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
530 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
536 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs")
[all...] |
| CodeGenSchedule.h | 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
49 Record *TheDef;
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
88 return TheDef || !Sequence.empty();
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| AsmMatcherEmitter.cpp | 403 /// TheDef - This is the definition of the instruction or InstAlias that this
405 Record *const TheDef;
442 : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI) {
446 : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef), DefRec(Alias.release()) {
572 Record *TheDef;
577 SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
581 return "Feature_" + TheDef->getName();
586 TheDef->dump()
[all...] |
| AsmWriterEmitter.cpp | 111 << FirstInst.CGI->TheDef->getName() << ":\n";
114 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
125 FirstInst.CGI->TheDef->getName(),
131 AWI.CGI->TheDef->getName(),
175 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
182 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
401 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
415 << NumberedInstructions->at(i)->TheDef->getName() << "\n";
540 AsmName = Reg.TheDef->getValueAsString("AsmName");
546 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices")
[all...] |
| CodeGenSchedule.cpp | 79 if (R.match(Inst->TheDef->getName()))
80 Elts.insert(Inst->TheDef);
217 Record *SchedDef = Inst->TheDef;
296 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
349 if (I->TheDef == Def)
357 Record *ReadDef = SchedReads[i].TheDef;
412 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
438 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
441 AliasDef = AliasRW.TheDef;
[all...] |
| CodeGenInstruction.h | 128 Record *TheDef; // The actual record containing this OperandList.
208 Record *TheDef; // The actual record defining this instruction.
290 Record *TheDef; // The actual record defining this InstAlias.
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| SubtargetEmitter.cpp | 664 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
665 return SchedWrite.TheDef;
672 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
673 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
678 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
681 AliasDef = AliasRW.TheDef;
693 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
707 + SchedWrite.TheDef->getName());
717 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
718 return SchedRead.TheDef;
[all...] |
| CodeGenRegisters.cpp | 34 : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) {
44 : TheDef(nullptr), Name(N), Namespace(Nspace), Size(-1), Offset(-1),
57 if (!TheDef)
60 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
63 PrintFatalError(TheDef->getLoc(),
69 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
73 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
76 PrintFatalError(TheDef->getLoc(),
107 : TheDef(R),
118 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices")
[all...] |
| CodeGenRegisters.h | 55 Record *const TheDef;
128 Record *TheDef;
142 // Extract more information from TheDef. This is used to build an object
276 Record *TheDef;
317 Record *getDef() const { return TheDef; }
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| CodeGenInstruction.cpp | 28 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
139 PrintFatalError("'" + TheDef->getName() +
159 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'");
169 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'");
179 PrintFatalError(TheDef->getName() + ": Illegal to refer to"
189 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
197 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
296 : TheDef(R), Operands(R), InferredFrom(nullptr) {
575 : TheDef(R) {
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| RegisterInfoEmitter.cpp | 79 Registers.front().TheDef->getValueAsString("Namespace");
329 Record *Reg = RE.TheDef;
347 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
396 Record *Reg = RE.TheDef;
449 Record *Reg = RE.TheDef;
457 std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");
[all...] |
| FixedLenDecoderEmitter.cpp | 368 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
376 AllInstructions[Opcode]->TheDef->getValueAsBitsInit("SoftFail");
388 return AllInstructions[Opcode]->TheDef->getName();
802 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n";
[all...] |
| PseudoLoweringEmitter.cpp | 212 << Source.TheDef->getName() << ": {\n"
216 << Dest.TheDef->getName() << ");\n";
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| CodeGenTarget.cpp | 322 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
438 TheDef = R;
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| CodeGenDAGPatterns.h | 765 if (Intrinsics[i].TheDef == R) return Intrinsics[i];
767 if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i];
781 if (Intrinsics[i].TheDef == R) return i;
783 if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size();
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| CodeEmitterGen.cpp | 246 Record *R = CGI->TheDef;
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| CodeGenMapTable.cpp | 375 Record *CurInstr = NumberedInstructions[i]->TheDef;
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| CodeGenDAGPatterns.cpp | [all...] |
| DAGISelMatcherEmitter.cpp | 460 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
465 OS << getQualifiedName(Reg->TheDef) << ",\n";
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| IntrinsicEmitter.cpp | 771 PrintFatalError("Intrinsic '" + Ints[i].TheDef->getName() +
827 PrintFatalError("Intrinsic '" + Intrinsic.TheDef->getName() + "': "
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| X86RecognizableInstr.cpp | 196 Rec = insn.TheDef;
270 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
[all...] |
| DAGISelMatcherGen.cpp | [all...] |
