| /external/llvm/include/llvm/CodeGen/ |
| LiveRegMatrix.h | 97 /// VirtReg is live across a call, and PhysReg isn't call-preserved.
101 /// Check for interference before assigning VirtReg to PhysReg.
102 /// If this function returns IK_Free, it is legal to assign(VirtReg, PhysReg).
105 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
107 /// Assign VirtReg to PhysReg.
108 /// This will mark VirtReg's live range as occupied in the LiveRegMatrix and
110 void assign(LiveInterval &VirtReg, unsigned PhysReg);
112 /// Unassign VirtReg from its PhysReg.
113 /// Assuming that VirtReg was previously assigned to a PhysReg, this undoes
115 void unassign(LiveInterval &VirtReg);
[all...] |
| LiveIntervalUnion.h | 87 void unify(LiveInterval &VirtReg, const LiveRange &Range);
88 void unify(LiveInterval &VirtReg) {
89 unify(VirtReg, VirtReg);
93 void extract(LiveInterval &VirtReg, const LiveRange &Range);
94 void extract(LiveInterval &VirtReg) {
95 extract(VirtReg, VirtReg);
113 LiveInterval *VirtReg;
114 LiveInterval::iterator VirtRegI; // current position in VirtReg
[all...] |
| VirtRegMap.h | 92 bool hasPhys(unsigned virtReg) const {
93 return getPhys(virtReg) != NO_PHYS_REG;
98 unsigned getPhys(unsigned virtReg) const {
99 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
100 return Virt2PhysMap[virtReg];
105 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
106 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
108 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
111 Virt2PhysMap[virtReg] = physReg;
116 void clearVirt(unsigned virtReg) {
[all...] |
| ScheduleDAGInstrs.h | 35 unsigned VirtReg;
38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
41 return TargetRegisterInfo::virtReg2Index(VirtReg);
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| RegisterPressure.h | 406 bool hasUntiedDef(unsigned VirtReg) const {
407 return UntiedDefs.count(VirtReg);
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| /external/llvm/lib/CodeGen/ |
| RegAllocBase.cpp | 88 while (LiveInterval *VirtReg = dequeue()) {
89 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned");
92 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
93 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n');
94 aboutToRemoveInterval(*VirtReg);
95 LIS->removeInterval(VirtReg->reg);
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
107 << ':' << *VirtReg << " w=" << VirtReg->weight << '\n');
110 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs)
[all...] |
| LiveRegMatrix.cpp | 99 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
100 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
102 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
103 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
106 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
109 Matrix[Unit].unify(VirtReg, Range);
117 void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
118 unsigned PhysReg = VRM->getPhys(VirtReg.reg);
119 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI
[all...] |
| AllocationOrder.cpp | 30 AllocationOrder::AllocationOrder(unsigned VirtReg,
36 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
|
| LiveIntervalUnion.cpp | 29 void LiveIntervalUnion::unify(LiveInterval &VirtReg, const LiveRange &Range) {
40 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
50 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
52 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
56 void LiveIntervalUnion::extract(LiveInterval &VirtReg, const LiveRange &Range) {
67 assert(SegPos.value() == &VirtReg && "Inconsistent LiveInterval");
104 bool LiveIntervalUnion::Query::isSeenInterference(LiveInterval *VirtReg) const {
106 std::find(InterferingVRegs.begin(), InterferingVRegs.end(), VirtReg);
130 if (VirtReg->empty() || LiveUnion->empty()) {
135 // In most cases, the union will start before VirtReg
[all...] |
| RegAllocFast.cpp | 72 unsigned VirtReg; // Virtual register number.
78 : LastUse(nullptr), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false){}
81 return TargetRegisterInfo::virtReg2Index(VirtReg);
113 // PhysRegState - One of the RegState enums, or a virtreg.
167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
172 void killVirtReg(unsigned VirtReg);
174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
180 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) {
181 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
183 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const
[all...] |
| RegAllocBasic.cpp | 102 unsigned selectOrSplit(LiveInterval &VirtReg,
111 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
164 // that interfere with VirtReg. The newly spilled or split live intervals are
166 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
174 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units);
180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight)
186 " interferences with " << VirtReg << "\n");
220 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg,
226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
229 switch (Matrix->checkInterference(VirtReg, PhysReg))
[all...] |
| RegisterCoalescer.h | 64 /// Create a CoalescerPair representing a virtreg-to-physreg copy.
66 CoalescerPair(unsigned VirtReg, unsigned PhysReg,
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| RegAllocGreedy.cpp | 197 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
198 return ExtraRegInfo[VirtReg.reg].Stage;
201 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
203 ExtraRegInfo[VirtReg.reg].Stage = Stage;
342 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
347 bool mayRecolorAllInterferences(unsigned PhysReg, LiveInterval &VirtReg,
358 unsigned calculateRegionSplitCost(LiveInterval &VirtReg,
363 unsigned doRegionSplit(LiveInterval &VirtReg, unsigned BestCand,
368 unsigned tryAssignCSRFirstTime(LiveInterval &VirtReg, AllocationOrder &Order,
476 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
[all...] |
| AllocationOrder.h | 34 /// Create a new AllocationOrder for VirtReg.
35 /// @param VirtReg Virtual register to allocate for.
38 AllocationOrder(unsigned VirtReg,
|
| RegAllocBase.h | 83 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
93 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
|
| VirtRegMap.cpp | 84 bool VirtRegMap::hasPreferredPhys(unsigned VirtReg) {
85 unsigned Hint = MRI->getSimpleHint(VirtReg);
90 return getPhys(VirtReg) == Hint;
93 bool VirtRegMap::hasKnownPreference(unsigned VirtReg) {
94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg);
102 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
103 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
104 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
106 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC)
[all...] |
| LiveDebugVariables.cpp | 309 /// lookupVirtReg - Find the EC leader for VirtReg or null.
310 UserValue *lookupVirtReg(unsigned VirtReg);
348 void mapVirtReg(unsigned VirtReg, UserValue *EC);
478 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
479 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
480 UserValue *&Leader = virtRegToEqClass[VirtReg];
484 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
485 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
934 unsigned VirtReg = Loc.getReg();
935 if (VRM.isAssignedReg(VirtReg) &
[all...] |
| TargetRegisterInfo.cpp | 265 TargetRegisterInfo::getRegAllocationHints(unsigned VirtReg,
271 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
283 // Check that Phys is a valid hint in VirtReg's register class.
289 // from VirtReg's register class if they aren't in the allocation order. The
|
| InlineSpiller.cpp | 856 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
862 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops);
868 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
874 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
[all...] |
| MachineBasicBlock.cpp | 359 unsigned VirtReg = I->getOperand(0).getReg();
360 if (!MRI.constrainRegClass(VirtReg, RC))
362 return VirtReg;
366 unsigned VirtReg = MRI.createVirtualRegister(RC);
367 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
371 return VirtReg;
[all...] |
| PHIElimination.cpp | 201 /// isImplicitlyDefined - Return true if all defs of VirtReg are implicit-defs.
203 static bool isImplicitlyDefined(unsigned VirtReg,
205 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
|
| MachineTraceMetrics.cpp | 616 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp)
618 assert(TargetRegisterInfo::isVirtualRegister(VirtReg));
619 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 125 void getRegAllocationHints(unsigned VirtReg,
|
| ARMBaseRegisterInfo.cpp | 224 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
230 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
241 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 679 /// VirtReg. These registers are effectively moved to the front of the
682 /// The Order argument is the allocation order for VirtReg's register class
690 /// order for VirtReg. There may be target-independent hints.
691 virtual void getRegAllocationHints(unsigned VirtReg,
[all...] |
