| /external/libavc/common/armv8/ |
| ih264_neon_macros.s | 36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
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| /external/libmpeg2/common/armv8/ |
| impeg2_neon_macros.s | 53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
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| /external/llvm/test/MC/MachO/ |
| bad-macro.s | 5 .macro test_macro reg1, reg2
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| /external/libunwind/src/ptrace/ |
| _UPT_access_mem.c | 63 long reg1, reg2;
64 reg1 = ptrace (PTRACE_PEEKDATA, pid, (void*) (uintptr_t) addr, 0);
70 *val = ((unw_word_t)(reg2) << 32) | (uint32_t) reg1;
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| /external/boringssl/src/crypto/perlasm/ |
| x86gas.pl | 70 { my($addr,$reg1,$reg2,$idx)=@_;
73 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
79 $reg1 = "%$reg1" if ($reg1);
86 $ret .= "($reg1,$reg2,$idx)";
88 elsif ($reg1)
89 { $ret .= "($reg1)"; }
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| x86masm.pl | 39 { my($size,$addr,$reg1,$reg2,$idx)=@_;
42 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
61 $ret .= "+$reg1" if ($reg1 ne "");
64 { $ret .= "$reg1"; }
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| x86nasm.pl | 36 { my($size,$addr,$reg1,$reg2,$idx)=@_;
39 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
62 $ret .= "+$reg1" if ($reg1 ne "");
65 { $ret .= "$reg1"; }
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| /art/compiler/dex/quick/arm64/ |
| int_arm64.cc | 615 RegLocation Arm64Mir2Lir::GenDivRemLit(RegLocation rl_dest, RegStorage reg1, int lit, bool is_div) {
623 rl_result = GenDivRem(rl_result, reg1, lit_temp, is_div);
1477 int reg1 = -1, reg2 = -1; local
1496 int reg1 = -1, reg2 = -1; local
1550 int reg1 = -1, reg2 = -1; local
1690 int reg1 = -1, reg2 = -1; local
1709 int reg1 = -1, reg2 = -1; local
[all...] |
| /external/mesa3d/src/mesa/program/ |
| register_allocate.c | 189 struct ra_reg *reg1 = ®s->regs[r1]; local
191 if (reg1->conflict_list_size == reg1->num_conflicts) {
192 reg1->conflict_list_size *= 2;
193 reg1->conflict_list = reralloc(regs->regs, reg1->conflict_list,
194 unsigned int, reg1->conflict_list_size);
196 reg1->conflict_list[reg1->num_conflicts++] = r2;
197 reg1->conflicts[r2] = GL_TRUE
[all...] |
| /art/compiler/dex/ |
| reg_storage.h | 280 static constexpr bool SameRegType(RegStorage reg1, RegStorage reg2) {
281 return ((reg1.reg_ & kShapeTypeMask) == (reg2.reg_ & kShapeTypeMask));
284 static constexpr bool SameRegType(int reg1, int reg2) {
285 return ((reg1 & kShapeTypeMask) == (reg2 & kShapeTypeMask));
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| /external/skia/gm/ |
| imageblur.cpp | 67 static GMRegistry reg1(MyFactory1);
|
| imageblurtiled.cpp | 77 static GMRegistry reg1(MyFactory1);
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| /art/compiler/utils/arm/ |
| assembler_arm_test.h | 71 template <typename Reg1, typename Reg2>
72 std::string RepeatTemplatedRRIIC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
73 const std::vector<Reg1*> reg1_registers,
75 std::string (AssemblerArmTest::*GetName1)(const Reg1&),
122 for (auto reg1 : reg1_registers) {
125 std::string reg1_string = (this->*GetName1)(*reg1);
147 (Base::GetAssembler()->*f)(*reg1, *reg2, i, j, c);
168 template <typename Reg1, typename Reg2>
169 std::string RepeatTemplatedRRiiC(void (Ass::*f)(Reg1, Reg2, Imm, Imm, Cond),
170 const std::vector<Reg1*> reg1_registers
[all...] |
| /art/compiler/utils/ |
| assembler_test.h | 371 template <typename Reg1, typename Reg2>
372 std::string RepeatTemplatedRegisters(void (Ass::*f)(Reg1, Reg2),
373 const std::vector<Reg1*> reg1_registers,
375 std::string (AssemblerTest::*GetName1)(const Reg1&),
381 for (auto reg1 : reg1_registers) {
383 (assembler_.get()->*f)(*reg1, *reg2);
386 std::string reg1_string = (this->*GetName1)(*reg1);
409 template <typename Reg1, typename Reg2>
410 std::string RepeatTemplatedRegistersImm(void (Ass::*f)(Reg1, Reg2, const Imm&),
411 const std::vector<Reg1*> reg1_registers
[all...] |
| /external/aac/libFDK/src/ |
| fixpoint_math.cpp | 430 FIXP_DBL reg1, reg2, regtmp ; local
445 reg1 = invSqrtTab[ (INT)(val>>(DFRACT_BITS-1-(SQRT_BITS+1))) & SQRT_BITS_MASK ];
448 regtmp= fPow2Div2(reg1); /* a = Q^2 */
450 reg1 += (fMultDiv2(regtmp, reg1)<<4); /* Q = Q + Q*b */
455 reg1 = fMultDiv2(reg1, reg2) << 2;
460 return(reg1);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 150 bool haveSameParity(unsigned reg1, unsigned reg2) {
151 assert(isFPReg(reg1) && "Expecting an FP register for reg1");
154 return isOdd(reg1) == isOdd(reg2);
|
| /external/v8/test/cctest/ |
| test-utils-arm64.cc | 148 const Register& reg1) {
149 DCHECK(reg0.Is64Bits() && reg1.Is64Bits());
151 int64_t result = core->xreg(reg1.code());
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| test-utils-arm64.h | 190 const Register& reg1);
|
| /external/vixl/test/ |
| test-utils-a64.cc | 180 const Register& reg1) {
181 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
183 int64_t result = core->xreg(reg1.code());
|
| test-utils-a64.h | 210 const Register& reg1);
|
| /external/v8/src/arm64/ |
| assembler-arm64.h | 410 Register GetAllocatableRegisterThatIsNotOneOf(Register reg1,
418 bool AreAliased(const CPURegister& reg1,
430 // arguments. At least one argument (reg1) must be valid (not NoCPUReg).
431 bool AreSameSizeAndType(const CPURegister& reg1,
448 explicit CPURegList(CPURegister reg1,
452 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
453 size_(reg1.SizeInBits()), type_(reg1.type()) {
454 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
[all...] |
| /external/libvpx/libvpx/vp9/common/arm/neon/ |
| vp9_idct32x32_add_neon.asm | 72 ; reg1 = output[first_offset]
78 LOAD_FROM_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
81 vld1.s16 {$reg1}, [r1]
84 ; (used) two registers ($reg1, $reg2)
88 ; output[first_offset] = reg1
94 STORE_IN_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
97 vst1.16 {$reg1}, [r1]
241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
276 vqrshrn.s32 $reg1, q8, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_idct32x32_add_neon.asm | 72 ; reg1 = output[first_offset]
78 LOAD_FROM_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
81 vld1.s16 {$reg1}, [r1]
84 ; (used) two registers ($reg1, $reg2)
88 ; output[first_offset] = reg1
94 STORE_IN_OUTPUT $prev_offset, $first_offset, $second_offset, $reg1, $reg2
97 vst1.16 {$reg1}, [r1]
241 DO_BUTTERFLY $regC, $regD, $regA, $regB, $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg4
276 vqrshrn.s32 $reg1, q8, #14
286 DO_BUTTERFLY_STD $first_constant, $second_constant, $reg1, $reg2, $reg3, $reg
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 532 Register reg1,
552 // reg1 - Used to hold the capacity mask of the dictionary.
558 GetNumberHash(reg0, reg1);
561 lw(reg1, FieldMemOperand(elements, SeededNumberDictionary::kCapacityOffset));
562 sra(reg1, reg1, kSmiTagSize);
563 Subu(reg1, reg1, Operand(1));
573 and_(reg2, reg2, reg1);
597 lw(reg1, FieldMemOperand(reg2, kDetailsOffset))
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | 537 Register reg1,
557 // reg1 - Used to hold the capacity mask of the dictionary.
563 GetNumberHash(reg0, reg1);
566 ld(reg1, FieldMemOperand(elements, SeededNumberDictionary::kCapacityOffset));
567 SmiUntag(reg1, reg1);
568 Dsubu(reg1, reg1, Operand(1));
578 and_(reg2, reg2, reg1);
602 ld(reg1, FieldMemOperand(reg2, kDetailsOffset))
[all...] |
