/external/clang/test/CodeGen/ |
ppc64-vector.c | 3 typedef short v2i16 __attribute__((vector_size (4))); typedef 13 v2i16 test_v2i16(v2i16 x)
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builtins-mips.c | 12 typedef short v2i16 __attribute__ ((vector_size(4))); typedef 17 v2i16 v2i16_r, v2i16_a, v2i16_b, v2i16_c; 352 v2i16_a = (v2i16) {0xffff, 0x2468}; 353 v2i16_b = (v2i16) {0x1234, 0x1111}; 356 v2i16_a = (v2i16) {0xffff, 0x2468}; 357 v2i16_b = (v2i16) {0x1234, 0x1111}; 392 v2i16_b = (v2i16) {0xffff, 0x1555}; 393 v2i16_c = (v2i16) {0x1234, 0x3322}; 397 v2i16_b = (v2i16) {0xffff, 0x1555}; 398 v2i16_c = (v2i16) {0x1234, 0x3322} [all...] |
systemz-abi-vector.c | 11 typedef __attribute__((vector_size(4))) short v2i16; typedef 54 v2i16 pass_v2i16(v2i16 arg) { return arg; }
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x86_32-arguments-darwin.c | 217 typedef unsigned short v2i16 __attribute__((__vector_size__(4))); typedef 221 v2i16 f54(v2i16 arg) { return arg+arg; }
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/external/llvm/include/llvm/CodeGen/ |
MachineValueType.h | 74 v2i16 = 27, // 2 x i16 enumerator in enum:llvm::MVT::SimpleValueType 210 return (SimpleTy == MVT::v4i8 || SimpleTy == MVT::v2i16 || 298 case v2i16: 361 case v2i16: 407 case v2i16: 545 if (NumElements == 2) return MVT::v2i16;
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/external/llvm/lib/Target/AArch64/ |
AArch64TargetTransformInfo.cpp | 201 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, 204 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, 215 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, 218 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 }, 232 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f32, 1 }, 235 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f32, 1 }, 246 { ISD::FP_TO_SINT, MVT::v2i16, MVT::v2f64, 2 }, 249 { ISD::FP_TO_UINT, MVT::v2i16, MVT::v2f64, 2 },
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AArch64ISelLowering.cpp | 428 // load, floating-point truncating stores, or v2i32->v2i16 truncating store. 584 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); [all...] |
/external/llvm/lib/IR/ |
ValueTypes.cpp | 145 case MVT::v2i16: return "v2i16"; 213 case MVT::v2i16: return VectorType::get(Type::getInt16Ty(Context), 2);
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/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 111 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 2 }, 142 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 }, 143 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 3 },
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ARMISelLowering.cpp | 574 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16, [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
AMDILISelLowering.cpp | 59 (int)MVT::v2i16, 87 (int)MVT::v2i16, 209 setOperationAction(ISD::UDIV, MVT::v2i16, Expand); 666 if (OVT == MVT::v2i16) {
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/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 167 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) { 248 } else if (LocVT == MVT::v4i8 || LocVT == MVT::v2i16) { [all...] |
/external/llvm/lib/Target/Mips/ |
MipsSEISelLowering.cpp | 60 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 84 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 876 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) [all...] |
/external/llvm/utils/TableGen/ |
CodeGenTarget.cpp | 87 case MVT::v2i16: return "MVT::v2i16";
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/external/llvm/lib/Target/R600/ |
AMDGPUISelLowering.cpp | 172 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); 234 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v2i16, Expand); 235 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v2i16, Expand); 236 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand); [all...] |
SIISelLowering.cpp | 116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); [all...] |
R600ISelLowering.cpp | 108 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Expand); [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 65 case MVT::v2i16: [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 617 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom); [all...] |