| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 373 {ISD::VECTOR_SHUFFLE, MVT::v8f32, 1}, // vblendps
497 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 1 },
499 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 },
567 { ISD::FP_EXTEND, MVT::v8f64, MVT::v8f32, 3 },
568 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 },
570 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 8 },
600 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i1, 8 },
601 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i8, 8 },
602 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 5 },
603 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 1 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 99 v8f32 = 48, // 8 x f32 enumerator in enum:llvm::MVT::SimpleValueType
233 return (SimpleTy == MVT::v8f32 || SimpleTy == MVT::v4f64 ||
319 case v8f32:
349 case v8f32:
437 case v8f32:
574 if (NumElements == 8) return MVT::v8f32;
|
| /external/clang/test/CodeGen/ |
| x86_64-arguments.c | 190 typedef float v8f32 __attribute__((__vector_size__(32))); typedef
192 v8f32 v;
201 v8f32 v[1];
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 120 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
121 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 },
122 { ISD::SINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
123 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i32, 2 },
149 { ISD::FP_TO_SINT, MVT::v8i16, MVT::v8f32, 4 },
150 { ISD::FP_TO_UINT, MVT::v8i16, MVT::v8f32, 4 },
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 171 DecodeBLENDMask(MVT::v8f32,
271 DecodeMOVSHDUPMask(MVT::v8f32, ShuffleMask);
279 DecodeMOVSLDUPMask(MVT::v8f32, ShuffleMask);
663 DecodeSHUFPMask(MVT::v8f32,
710 DecodeUNPCKLMask(MVT::v8f32, ShuffleMask);
762 DecodeUNPCKHMask(MVT::v8f32, ShuffleMask);
789 DecodePSHUFMask(MVT::v8f32,
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 166 case MVT::v8f32: return "v8f32";
234 case MVT::v8f32: return VectorType::get(Type::getFloatTy(Context), 8);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 108 case MVT::v8f32: return "MVT::v8f32";
|
| /external/llvm/lib/Target/R600/ |
| AMDGPUISelLowering.cpp | 156 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
157 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
196 setOperationAction(ISD::LOAD, MVT::v8f32, Promote);
197 AddPromotedToType(ISD::LOAD, MVT::v8f32, MVT::v8i32);
211 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom);
216 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v8f32, Custom);
[all...] |
| SIISelLowering.cpp | 58 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
178 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32}) {
[all...] |
