| /external/llvm/test/MC/Disassembler/Mips/mips64r3/ |
| valid-mips64r3.txt | 22 0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r5/ |
| valid-mips64r5-el.txt | 22 0x4c 0x01 0xc0 0x18 # CHECK: blez $6, 1332
|
| valid-mips64r5.txt | 22 0x18 0xc0 0x01 0x4c # CHECK: blez $6, 1332
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.h | 367 void BLEZ(int Rs, const char* label);
|
| mips_disassem.c | 69 /* 0 */ "spec", "bcond","j ", "jal", "beq", "bne", "blez", "bgtz",
|
| MIPSAssembler.cpp | [all...] |
| /bionic/libc/arch-mips/string/ |
| memcpy.S | 588 blez a2,L(leave)
|
| /external/llvm/lib/Target/Mips/ |
| MicroMipsInstrInfo.td | 811 def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>,
[all...] |
| Mips64InstrInfo.td | 218 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
|
| MipsInstrInfo.td | [all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 321 BLEZ = ((0 << 3) + 6) << kOpcodeShift,
|
| macro-assembler-mips.cc | [all...] |
| assembler-mips.h | 667 void blez(Register rs, int16_t offset);
[all...] |
| simulator-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 286 BLEZ = ((0 << 3) + 6) << kOpcodeShift,
|
| macro-assembler-mips64.cc | [all...] |
| assembler-mips64.h | 658 void blez(Register rs, int16_t offset);
[all...] |
| simulator-mips64.cc | [all...] |
| /art/compiler/dex/quick/mips/ |
| assemble_mips.cc | 136 NEEDS_FIXUP, "blez", "!0r,!1t!0N", 8),
[all...] |
| mips_lir.h | 572 kMipsBlez, // blez s,o [000110] s[25..21] [00000] o[15..0].
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_tilegx_toIR.c | 702 case 44: /* "blez" */
[all...] |
| host_mips_defs.c | [all...] |
| tilegx_disasm.c | 885 { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | [all...] |
| /external/pcre/dist/sljit/ |
| sljitNativeTILEGX-encoder.c | [all...] |
