| /external/vixl/src/vixl/a64/ |
| instrument-a64.cc | 87 {"Instruction", Cumulative},
150 // Dump any remaining instruction data to the output file.
166 // Increment the instruction counter, and dump all counters if a sample period
168 static Counter* counter = GetCounter("Instruction");
214 static Counter* counter = GetCounter("Instruction");
256 void Instrument::VisitPCRelAddressing(const Instruction* instr) {
264 void Instrument::VisitAddSubImmediate(const Instruction* instr) {
272 void Instrument::VisitLogicalImmediate(const Instruction* instr) {
280 void Instrument::VisitMoveWideImmediate(const Instruction* instr) {
293 void Instrument::VisitBitfield(const Instruction* instr)
[all...] |
| /art/compiler/optimizing/ |
| graph_checker_test.cc | 75 Instruction::RETURN_VOID);
82 Instruction::GOTO | 0x100,
83 Instruction::RETURN_VOID);
90 Instruction::CONST_4 | 0 | 0,
91 Instruction::IF_EQ, 3,
92 Instruction::GOTO | 0x100,
93 Instruction::RETURN_VOID);
100 Instruction::CONST_4 | 0 | 0,
101 Instruction::IF_EQ, 3,
102 Instruction::GOTO | 0x100
[all...] |
| /external/llvm/test/MC/ARM/ |
| vorr-vbic-illegal-cases.s | 11 @ CHECK: error: invalid operand for instruction
13 @ CHECK: error: invalid operand for instruction
15 @ CHECK: error: invalid operand for instruction
17 @ CHECK: error: invalid operand for instruction
19 @ CHECK: error: invalid operand for instruction
21 @ CHECK: error: invalid operand for instruction
31 @ CHECK: error: invalid operand for instruction
33 @ CHECK: error: invalid operand for instruction
35 @ CHECK: error: invalid operand for instruction
37 @ CHECK: error: invalid operand for instruction
[all...] |
| crc32-thumb.s | 11 @ CHECK-V7: error: instruction requires: crc armv8
12 @ CHECK-V7: error: instruction requires: crc armv8
13 @ CHECK-V7: error: instruction requires: crc armv8
14 @ CHECK-NOCRC: error: instruction requires: crc
15 @ CHECK-NOCRC: error: instruction requires: crc
16 @ CHECK-NOCRC: error: instruction requires: crc
25 @ CHECK-V7: error: instruction requires: crc armv8
26 @ CHECK-V7: error: instruction requires: crc armv8
27 @ CHECK-V7: error: instruction requires: crc armv8
28 @ CHECK-NOCRC: error: instruction requires: cr
[all...] |
| crc32.s | 11 @ CHECK-V7: error: instruction requires: crc armv8
12 @ CHECK-V7: error: instruction requires: crc armv8
13 @ CHECK-V7: error: instruction requires: crc armv8
14 @ CHECK-NOCRC: error: instruction requires: crc
15 @ CHECK-NOCRC: error: instruction requires: crc
16 @ CHECK-NOCRC: error: instruction requires: crc
25 @ CHECK-V7: error: instruction requires: crc armv8
26 @ CHECK-V7: error: instruction requires: crc armv8
27 @ CHECK-V7: error: instruction requires: crc armv8
28 @ CHECK-NOCRC: error: instruction requires: cr
[all...] |
| udf-thumb-2-diagnostics.s | 10 @ CHECK: error: instruction 'udf' is not predicable, but condition code specified
16 @ CHECK: error: instruction requires: arm-mode
22 @ CHECK: error: invalid operand for instruction
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips1.s | 8 add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 c.sf.d $f30,$f0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 c.sf.s $f14,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 mfhi $s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 mfhi $sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mflo $s1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips2.s | 8 addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1fl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bc1fl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bc1tl $fcc0,-8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 bc1tl -8239 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 beql $14,$s3,12544 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 bnel $gp,$s4,5107 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 bgezl $4,-6858 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 bgtzl $10,-3738 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 blezl $6,2974 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| invalid-mips4-wrong-error.s | 9 bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| MethodAnalyzer.java | 40 import org.jf.dexlib2.iface.instruction.*;
41 import org.jf.dexlib2.iface.instruction.formats.*;
46 import org.jf.dexlib2.immutable.instruction.*;
80 // This contains all the AnalyzedInstruction instances, keyed by the code unit address of the instruction
84 // Which instructions have been analyzed, keyed by instruction index
89 //This is a dummy instruction that occurs immediately before the first real instruction. We can initialize the
90 //register types for this instruction to the parameter types, in order to have them propagate to all of its
91 //successors, e.g. the first real instruction, the first instructions in any exception handlers covering the first
92 //instruction, etc
248 Instruction instruction = analyzedInstruction.getInstruction(); local
[all...] |
| /external/proguard/src/proguard/optimize/evaluation/ |
| EvaluationSimplifier.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
146 Instruction instruction = InstructionFactory.create(codeAttribute.code, local
149 instruction.accept(clazz, method, codeAttribute, offset, this);
407 * Replaces the push instruction at the given offset by a simpler push
408 * instruction, if possible.
412 Instruction instruction)
420 replaceIntegerPushInstruction(clazz, offset, instruction);
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCWin64EH.h | 27 struct Instruction {
28 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) {
29 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1);
31 static WinEH::Instruction Alloc(MCSymbol *L, unsigned Size) {
32 return WinEH::Instruction(Size > 128 ? UOP_AllocLarge : UOP_AllocSmall, L,
35 static WinEH::Instruction PushMachFrame(MCSymbol *L, bool Code) {
36 return WinEH::Instruction(UOP_PushMachFrame, L, -1, Code ? 1 : 0);
38 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg,
40 return WinEH::Instruction(Offset > 512 * 1024 - 8 ? UOP_SaveNonVolBig
44 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg
[all...] |
| /external/valgrind/docs/internals/ |
| s390-opcodes.csv | 2 ad,"add normalized (long)","won't do","hfp instruction"
3 adr,"add normalized (long)","won't do","hfp instruction"
4 ae,"add normalized (short)","won't do","hfp instruction"
5 aer,"add normalized (short)","won't do","hfp instruction"
11 au,"add unnormalized (short)","won't do","hfp instruction"
12 aur,"add unnormalized (short)","won't do","hfp instruction"
13 aw,"add unnormalized (long)","won't do","hfp instruction"
14 awr,"add unnormalized (long)","won't do","hfp instruction"
15 axr,"add normalized","won't do","hfp instruction"
31 cd,"compare (long)","won't do","hfp instruction"
[all...] |
| /external/llvm/test/MC/Mips/mips32/ |
| invalid-mips32r2.s | 8 cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 ldxc1 $f8,$s7($t7) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/proguard/src/proguard/classfile/editor/ |
| InstructionWriter.java | 26 import proguard.classfile.instruction.*;
27 import proguard.classfile.instruction.visitor.InstructionVisitor;
89 // Try to write out the instruction.
99 // Try to write out the instruction.
104 // Create a new constant instruction that will fit.
105 Instruction replacementInstruction =
117 // Write out a dummy constant instruction for now.
129 // Try to write out the instruction.
134 // Create a new variable instruction that will fit.
135 Instruction replacementInstruction
[all...] |
| InstructionAdder.java | 25 import proguard.classfile.instruction.*;
26 import proguard.classfile.instruction.visitor.InstructionVisitor;
58 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction)
60 // Add the instruction.
61 codeAttributeComposer.appendInstruction(offset, instruction);
67 // Create a copy of the instruction.
68 Instruction newConstantInstruction =
73 // Add the instruction.
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| basic-a64-undefined.txt | 11 # CHECK: invalid instruction encoding
12 # CHECK: invalid instruction encoding
13 # CHECK: invalid instruction encoding
21 # CHECK: invalid instruction encoding
22 # CHECK: invalid instruction encoding
23 # CHECK: invalid instruction encoding
24 # CHECK: invalid instruction encoding
30 # CHECK: invalid instruction encoding
31 # CHECK: invalid instruction encoding
37 # CHECK: invalid instruction encodin
[all...] |
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips64r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 drotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 drotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 drotr32 $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 drotr32 $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 drotrv $1,$14,$15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
17 mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enable
[all...] |
| /external/valgrind/none/tests/mips64/ |
| macro_int.h | 1 #define TEST1(instruction, RSval, RTval, RD, RS, RT) \
8 instruction "\n\t" \
15 instruction, out, (long long) RSval, \
19 #define TEST2(instruction, RSval, imm, RT, RS) \
25 instruction "\n\t" \
32 instruction, out, (long long) RSval, imm); \
35 #define TEST3(instruction, RSval, RD, RS) \
41 instruction "\n\t" \
48 instruction, out, (long long) RSval); \
51 #define TEST4(instruction, RSval, RTval, RS, RT)
[all...] |
| /external/llvm/test/MC/Mips/mips64r6/ |
| invalid-mips4.s | 8 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
16 swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4-wrong-error.s | 9 bc2tl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
10 bc2fl 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
11 prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.h | 45 virtual bool insnCanLoad(const Instruction *insn, int s,
46 const Instruction *ld) const;
49 virtual bool isModSupported(const Instruction *, int s, Modifier) const;
50 virtual bool isSatSupported(const Instruction *) const;
52 virtual bool mayPredicate(const Instruction *, const Value *) const;
54 virtual bool canDualIssue(const Instruction *, const Instruction *) const;
55 virtual int getLatency(const Instruction *) const;
56 virtual int getThroughput(const Instruction *) const;
|
| /external/proguard/src/proguard/classfile/instruction/ |
| SwitchInstruction.java | 21 package proguard.classfile.instruction;
24 * This Instruction represents a simple instruction without variable arguments
29 public abstract class SwitchInstruction extends Instruction
55 * Copies the given instruction into this instruction.
56 * @param switchInstruction the instruction to be copied.
57 * @return this instruction.
69 // Implementations for Instruction.
|
| /external/llvm/test/MC/AArch64/ |
| arm64-v128_lo-diagnostics.s | 5 // CHECK: error: invalid operand for instruction
8 // CHECK: error: invalid operand for instruction
11 // CHECK: error: invalid operand for instruction
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-virtexts.arm.txt | 5 # CHECK-ARM: warning: invalid instruction encoding
9 # CHECK-ARM: warning: potentially undefined instruction encoding
10 # CHECK-ARM: warning: potentially undefined instruction encoding
|
