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  /external/llvm/test/CodeGen/AArch64/
fast-isel-switch-phi.ll 3 ; Test that the Machine Instruction PHI node doesn't have more than one operand
  /external/llvm/test/CodeGen/ARM/
2011-08-12-vmovqqqq-pseudo.ll 2 ; Make sure that the VMOVQQQQ pseudo instruction is handled properly
2012-10-04-LDRB_POST_IMM-Crash.ll 2 ; Check that LDRB_POST_IMM instruction emitted properly.
peephole-bitcast.ll 8 ; Peephole leaves a dead vmovsr instruction behind, and depends on linear scan
  /external/llvm/test/CodeGen/Hexagon/
fusedandshift.ll 2 ; Check that we generate fused logical and with shift instruction.
  /external/llvm/test/CodeGen/R600/
icmp-select-sete-reverse-args.ll 4 ;to a SETNE_INT. There should only be one SETNE_INT instruction.
insert_subreg.ll 5 ; instruction selection.
legalizedag-bug-expand-setcc.ll 7 ; This bug caused the icmp IR instruction to be expanded to two machine
selectcc-icmp-select-float.ll 4 ; CND* instruction.
vtx-schedule.ll 4 ; the result of another VTX_READ instruction were being grouped in the
  /external/llvm/test/CodeGen/Thumb2/
thumb2-bcc.ll 3 ; generation, so use memory barrier instruction to make sure it doesn't
  /external/llvm/test/CodeGen/X86/
2003-08-03-CallArgLiveRanges.ll 2 ; The old instruction selector used to load all arguments to a call up in
dag-optnone.ll 6 ; and we said -O0) but as a practical matter there are some instruction
12 ; re-enabled in r233153 because of problems with instruction selection patterns
16 ; If instruction selection eventually becomes smart enough to run without DAG
57 ; The test case @bar is derived from an instruction selection failure case
ga-offset.ll 10 ; This store should fold to a single mov instruction.
  /external/llvm/test/MC/AArch64/
arm64-separator.s 10 ; there is one for each 'mov' instruction.
  /external/llvm/test/MC/ARM/
directive-thumb_func.s 21 // CHECK-EABI-NOT: error: invalid instruction
thumb2-bxj.s 10 @ UNDEF: error: instruction requires: arm-mode
  /external/llvm/test/MC/AsmParser/
comments-x86-darwin.s 7 movl %esp, %ebp # same after an instruction
  /external/llvm/test/MC/Disassembler/AArch64/
ldp-postind.predictable.txt 6 # CHECK-NOT: potentially undefined instruction encoding
ldp-preind.predictable.txt 6 # CHECK-NOT: potentially undefined instruction encoding
  /external/llvm/test/MC/Disassembler/ARM/
invalid-IT-CC15.txt 12 # printing the final instruction in this list.
virtexts-thumb.txt 12 # CHECK-NOVIRT: warning: invalid instruction encoding
13 # CHECK-NOVIRT: warning: invalid instruction encoding
14 # CHECK-NOVIRT: warning: invalid instruction encoding
15 # CHECK-NOVIRT: warning: invalid instruction encoding
  /external/llvm/test/MC/ELF/
relax-all-flag.s 4 // expect to see a different instruction.
  /external/llvm/test/MC/MachO/ARM/
thumb-bl-jbits.s 15 # We are checking that the branch and link instruction which is:
  /external/llvm/test/MC/Mips/mips64r6/
invalid.s 12 ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled

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