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  /external/smali/dexlib2/src/main/java/org/jf/dexlib2/iface/instruction/formats/
ArrayPayload.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.PayloadInstruction;
Instruction10t.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
Instruction11x.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OneRegisterInstruction;
Instruction12x.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction20t.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
Instruction22x.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
Instruction23x.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.ThreeRegisterInstruction;
Instruction30t.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
Instruction32x.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.TwoRegisterInstruction;
PackedSwitchPayload.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.SwitchPayload;
SparseSwitchPayload.java 32 package org.jf.dexlib2.iface.instruction.formats;
34 import org.jf.dexlib2.iface.instruction.SwitchPayload;
  /external/v8/src/mips/
constants-mips.h 17 #define UNSUPPORTED_MIPS() v8::internal::PrintF("Unsupported instruction.\n")
119 // Volume II: The MIPS32 Instruction Set
171 // 'pref' instruction hints
294 // Instruction bit masks.
312 // MIPS32 Architecture For Programmers, Volume II: The MIPS32 Instruction Set.
726 // A nop instruction. (Encoding of sll 0 0 0).
729 class Instruction {
735 // always the value of the current instruction being executed.
739 // Get the raw instruction bits.
744 // Set the raw instruction bits to value
    [all...]
  /external/llvm/lib/Target/X86/
X86FastISel.cpp 68 bool fastSelectInstruction(const Instruction *I) override;
71 /// vreg is being provided by the specified load instruction. If possible,
72 /// try to fold the load as an operand to the instruction, returning true if
101 bool X86SelectLoad(const Instruction *I);
103 bool X86SelectStore(const Instruction *I);
105 bool X86SelectRet(const Instruction *I);
107 bool X86SelectCmp(const Instruction *I);
109 bool X86SelectZExt(const Instruction *I);
111 bool X86SelectBranch(const Instruction *I);
113 bool X86SelectShift(const Instruction *I)
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  /external/llvm/include/llvm/Analysis/
ConstantFolding.h 26 class Instruction;
34 /// ConstantFoldInstruction - Try to constant fold the specified instruction.
39 Constant *ConstantFoldInstruction(Instruction *I, const DataLayout &DL,
49 /// ConstantFoldInstOperands - Attempt to constant fold an instruction with the
61 /// instruction (icmp/fcmp) with the specified operands. If it fails, it
70 /// instruction with the specified operands and indices. The constant result is
  /external/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 16 // Walking the instruction list linearly will get many, perhaps most, of
30 // instruction, whichever is less. Our optimization is then a graph problem
71 // instruction should be transformed to its equivalent AdvSIMD scalar
72 // instruction. "add Xd, Xn, Xm" ==> "add Dd, Da, Db", for example.
75 // transformInstruction - Perform the transformation of an instruction
76 // to its equivalant AdvSIMD scalar instruction. Update inputs and outputs
123 // copy instruction. Return zero_reg if the instruction is not a copy.
128 // The "FMOV Xd, Dn" instruction is the typical form.
138 // Or just a plain COPY instruction. This can be directly to/from FPR64
    [all...]
AArch64CleanupLocalDynamicTLSPass.cpp 55 // when the first such instruction is seen, and then use it
90 // Replace the TLS_base_addr instruction I with a copy from
91 // TLSBaseAddrReg, returning the new instruction.
103 // Erase the TLS_base_addr instruction.
110 // inserting a copy instruction after I. Returns the new instruction.
  /external/llvm/lib/Target/Mips/
MipsInstrInfo.h 1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
14 // assembly. The returned value doesn't have to be the asm instruction's exact
75 /// Insert nop instruction when hazard condition is found
80 /// such, whenever a client has an instance of instruction info, it should
87 /// Return the number of bytes of code the specified instruction may be.
124 /// Create an instruction which has the same operands and memory operands
  /external/llvm/lib/Target/SystemZ/
SystemZLDCleanup.cpp 83 // when the first such instruction is seen, and then use it
112 // Replace the TLS_LDCALL instruction I with a copy from TLSBaseAddrReg,
113 // returning the new instruction.
121 // Erase the TLS_LDCALL instruction.
128 // inserting a copy instruction after I. Returns the new instruction.
  /external/llvm/lib/Transforms/Scalar/
IndVarSimplify.cpp 195 static Instruction *getInsertPointForUses(Instruction *User, Value *Def,
201 Instruction *InsertPt = nullptr;
215 assert((!isa<Instruction>(Def) ||
216 DT->dominates(cast<Instruction>(Def), InsertPt)) &&
262 if (Incr == nullptr || Incr->getOpcode() != Instruction::FAdd) return;
275 Instruction *U1 = cast<Instruction>(*IncrUse++);
277 Instruction *U2 = cast<Instruction>(*IncrUse++)
    [all...]
LoopInstSimplify.cpp 1 //===- LoopInstSimplify.cpp - Loop Instruction Simplification Pass --------===//
10 // This pass performs lightweight instruction simplification on loop bodies.
89 SmallPtrSet<const Instruction*, 8> S1, S2, *ToSimplify = &S1, *Next = &S2;
115 Instruction *I = BI++;
129 Next->insert(cast<Instruction>(U));
139 // more than one instruction, so simply incrementing the
  /external/llvm/test/TableGen/
TargetInstrInfo.td 7 class Instruction { // Would have other stuff eventually
61 Format f, list<dag> rtl> : Instruction {
70 // Start of instruction definitions, the real point of this file.
80 // 4. We capture the behavior of the instruction with a simplified RTL-like
86 // Simple copy instruction.
121 // Alternatively, if each tmporary register is only used once, the instruction
  /external/mesa3d/src/gallium/drivers/radeon/
R600ExpandSpecialInstrs.cpp 9 // Vector, Reduction, and Cube instructions need to fill the entire instruction
11 // into several instructions that will completely fill the instruction group.
70 // Expand the instruction
122 // Mask the write if the original instruction does not write to
132 // Add the new instruction
143 assert(!"Unknown CUBE instruction");
R600InstrInfo.h 1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
54 /// instruction slots within an instruction group.
113 ///hasFlagOperand - Returns true if this instruction has an operand for
123 ///getFlagOp - Return the operand containing the flags for this instruction.
126 ///clearFlag - Clear the specified flag on the instruction.
  /external/proguard/src/proguard/classfile/editor/
VariableRemapper.java 30 import proguard.classfile.instruction.*;
31 import proguard.classfile.instruction.visitor.InstructionVisitor;
184 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
194 // Replace the instruction.
195 Instruction replacementInstruction =
  /external/proguard/src/proguard/optimize/evaluation/
SimpleEnumClassSimplifier.java 28 import proguard.classfile.instruction.*;
29 import proguard.classfile.instruction.visitor.InstructionVisitor;
91 private static final Instruction[] INSTRUCTIONS = new Instruction[]
100 private static final Instruction[] REPLACEMENT_INSTRUCTIONS = new Instruction[]

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