| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 1 //===-- ExpandPostRAPseudos.cpp - Pseudo instruction expansion pass -------===//
62 "Post-RA pseudo instruction expansion pass", false, false)
64 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered
66 /// operands from MI to the replacement instruction.
109 // No need to insert an identity copy instruction.
151 // No need to insert an identity copy instruction, but replace with a KILL
155 // instruction with KILL.
|
| TargetInstrInfo.cpp | 1 //===-- TargetInstrInfo.cpp - Target Instruction Information --------------===//
61 /// insertNoop - Insert a noop into the instruction stream at the specified
71 /// count as an instruction.
72 /// Any other non-whitespace text is considered an instruction, with
99 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
127 // No idea how to commute this instruction. Target should implement its own.
160 // Create a new instruction.
179 /// operand indices that would swap value. Return true if the instruction
337 "Instruction cannot be duplicated");
341 // If the COPY instruction in MI can be folded to a stack operation, retur
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| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.h | 51 // Corresponds to retsp instruction
54 // Corresponds to LADD instruction
57 // Corresponds to LSUB instruction
60 // Corresponds to LMUL instruction
63 // Corresponds to MACCU instruction
66 // Corresponds to MACCS instruction
69 // Corresponds to CRC8 instruction
|
| /external/llvm/lib/Transforms/Scalar/ |
| StraightLineStrengthReduce.cpp | 93 Instruction *I)
103 // The instruction this candidate corresponds to. It helps us to rewrite a
104 // candidate with respect to its immediate basis. Note that one instruction
117 Instruction *Ins;
157 void allocateCandidatesAndFindBasis(Instruction *I);
159 void allocateCandidatesAndFindBasisForAdd(Instruction *I);
163 Instruction *I);
165 void allocateCandidatesAndFindBasisForMul(Instruction *I);
169 Instruction *I);
176 Instruction *I)
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| /external/v8/src/arm/ |
| assembler-arm.cc | 227 // specially coded on ARM means that it is a movw/movt instruction, or is an
402 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r))
406 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r))
516 return Instruction::ConditionField(instr);
618 reg.code_ = Instruction::RdValue(instr);
625 reg.code_ = Instruction::RnValue(instr);
632 reg.code_ = Instruction::RmValue(instr);
686 // Check the instruction is indeed a
693 // Check the instruction is indeed a
700 // Check the instruction is indeed
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| /external/llvm/docs/ |
| LangRef.rst | 51 instruction is syntactically okay, but not well formed:
138 demonstrating instructions, we will follow an instruction with a comment
654 and ends with a :ref:`terminator <terminators>` instruction (such as a branch or
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| /art/compiler/dex/quick/arm64/ |
| int_arm64.cc | 71 void Arm64Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest,
75 case Instruction::SHL_LONG:
76 case Instruction::SHL_LONG_2ADDR:
79 case Instruction::SHR_LONG:
80 case Instruction::SHR_LONG_2ADDR:
83 case Instruction::USHR_LONG:
84 case Instruction::USHR_LONG_2ADDR:
325 // Copies involving the sp register require a different instruction.
328 // TODO(Arm64): kA64Add4RRdT formally has 4 args, but is used as a 2 args instruction.
416 bool Arm64Mir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div
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| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_ra.cpp | 227 void condenseDefs(Instruction *);
228 void condenseSrcs(Instruction *, const int first, const int last);
230 void addHazard(Instruction *i, const ValueRef *src);
232 void addConstraint(Instruction *, int s, int n);
233 bool detectConflict(Instruction *, int s);
240 std::list<Instruction *> constrList;
284 LValue *unspill(Instruction *usei, LValue *, Value *slot);
285 void spill(Instruction *defi, Value *slot, LValue *);
293 Instruction *insn = val->getUniqueInsn();
337 Instruction *phi, *mov
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| /art/disassembler/ |
| disassembler_mips.cc | 35 bool Matches(uint32_t instruction) const {
36 return (instruction & mask) == value;
321 uint32_t instruction = ReadU32(instr_ptr); local
323 uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type.
324 uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type.
325 uint32_t rd = (instruction >> 11) & 0x1f; // R-type.
326 uint32_t sa = (instruction >> 6) & 0x1f; // R-type.
332 uint32_t op = (instruction >> 26) & 0x3f;
333 uint32_t function = (instruction & 0x3f); // R-type.
337 if (gMipsInstructions[i].Matches(instruction)) {
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| /external/libunwind/doc/ |
| libunwind-dynamic.man | 27 (typically the instruction\-pointer and the
36 information needed to reconstruct the frame\-state for each instruction
91 Within a region, each instruction that affects the frame state in some
93 purpose, each instruction in the region is assigned a unique index.
97 contrast, most CISC use variable\-length instruction encodings, so it
99 instruction index, the operation descriptor specifies the effect of
100 the instruction in an abstract manner. For example, it might express
101 that the instruction stores calle\-saved register r1
289 each instruction in the region affects the frame state. Of course,
303 instructions. Each instruction is assumed to have a fixed size (see
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| libunwind-dynamic.tex | 16 \emph{frame registers} (typically the instruction-pointer and the
24 information needed to reconstruct the frame-state for each instruction
71 Within a region, each instruction that affects the frame state in some
73 purpose, each instruction in the region is assigned a unique index.
77 contrast, most CISC use variable-length instruction encodings, so it
79 instruction index, the operation descriptor specifies the effect of
80 the instruction in an abstract manner. For example, it might express
81 that the instruction stores calle-saved register \Var{r1} at offset 16
216 each instruction in the region affects the frame state. Of course,
225 instructions. Each instruction is assumed to have a fixed size (se
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| /external/llvm/lib/IR/ |
| ConstantsContext.h | 82 : ConstantExpr(C2->getType(), Instruction::Select, &Op<0>(), 3) {
104 Instruction::ExtractElement, &Op<0>(), 2) {
124 : ConstantExpr(C1->getType(), Instruction::InsertElement,
149 Instruction::ShuffleVector,
172 : ConstantExpr(DestTy, Instruction::ExtractValue, &Op<0>(), 1),
197 : ConstantExpr(DestTy, Instruction::InsertValue, &Op<0>(), 2),
243 CompareConstantExpr(Type *ty, Instruction::OtherOps opc,
480 if (Instruction::isCast(Opcode))
482 if ((Opcode >= Instruction::BinaryOpsBegin &&
483 Opcode < Instruction::BinaryOpsEnd)
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| /external/llvm/lib/Transforms/Utils/ |
| SSAUpdater.cpp | 167 if (const Instruction *I = BB->getFirstNonPHI())
179 Instruction *User = cast<Instruction>(U.getUser());
196 Instruction *User = cast<Instruction>(U.getUser());
263 /// CreateEmptyPHI - Create a new PHI instruction in the specified block.
278 /// InstrIsPHI - Check if an instruction is a PHI.
280 static PHINode *InstrIsPHI(Instruction *I) {
299 /// GetPHIValue - For the specified PHI instruction, return the value
325 LoadAndStorePromoter(const SmallVectorImpl<Instruction*> &Insts
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow.c | 181 * the instruction.
239 * Also, the writemask of the instruction is not taken into account.
283 * Calls a callback function for all register writes in the instruction,
317 * and the writemask of the instruction is not taken into account.
439 * and update the given instruction \p inst accordingly
728 * readers we jump to the BGNLOOP instruction
729 * and check each instruction until we get
823 * encounters an instruction that reads from @param writer and also a different
824 * instruction. Here are some examples:
826 * writer = instruction 0
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| /prebuilts/tools/common/m2/repository/net/sf/proguard/proguard-base/4.10/ |
| proguard-base-4.10-sources.jar | |
| /prebuilts/tools/common/m2/repository/net/sf/proguard/proguard-base/4.11/ |
| proguard-base-4.11-sources.jar | |
| /prebuilts/tools/common/m2/repository/net/sf/proguard/proguard-base/4.9/ |
| proguard-base-4.9-sources.jar | |
| /prebuilts/tools/common/m2/repository/net/sf/proguard/proguard-base/5.1/ |
| proguard-base-5.1-sources.jar | |
| /prebuilts/tools/common/m2/repository/net/sf/proguard/proguard-base/5.2.1/ |
| proguard-base-5.2.1-sources.jar | |
| /prebuilts/tools/common/offline-m2/net/sf/proguard/proguard-base/5.1/ |
| proguard-base-5.1-sources.jar | |
| /art/compiler/dex/ |
| mir_graph.h | 242 static uint32_t GetStartUseIndex(Instruction::Code opcode);
262 Instruction::Code opcode;
264 explicit DecodedInstruction():vA(0), vB(0), vB_wide(0), vC(0), opcode(Instruction::NOP) {
268 * Given a decoded instruction representing a const bytecode, it updates
273 static bool IsPseudoMirOp(Instruction::Code opcode) {
282 return ((FlagsOf() & Instruction::kInvoke) == Instruction::kInvoke);
286 return ((FlagsOf() & Instruction::kStore) == Instruction::kStore);
290 return ((FlagsOf() & Instruction::kLoad) == Instruction::kLoad)
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| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 320 // Get the instruction.
322 // Get the instruction's basic block.
329 // Get the instruction info.
427 // Discard the DYNALLOC instruction.
441 // Get the instruction.
443 // Get the instruction's basic block.
480 // Discard the pseudo instruction.
486 // Get the instruction.
488 // Get the instruction's basic block.
523 // Discard the pseudo instruction
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| /external/llvm/lib/Target/X86/ |
| X86InstrFormats.td | 1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
11 // X86 Instruction Format Definitions.
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
59 // ImmType - This specifies the immediate type used by an instruction. This is
60 // part of the ad-hoc solution used to emit machine instruction encodings by our
75 // FPFormat - This specifies what form this FP instruction has. This is used by
224 : Instruction {
236 // If this is a pseudo instruction, mark it isCodeGenOnly.
244 bit ForceDisassemble = 0; // Force instruction to disassemble even though it'
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| /external/llvm/utils/TableGen/ |
| CodeGenMapTable.cpp | 1 //===- CodeGenMapTable.cpp - Instruction Mapping Table Generator ----------===//
30 // that can be used to retrieve the predicated form of the instruction by
32 // instruction as arguments.
44 // sort of relationship with the key instruction defined by the corresponding
70 // 4) For each key instruction, get the group of instructions that share the
71 // same key-value as the key instruction from RowInstrMap. Iterate over the list
74 // instruction from the group that matches all the values for the column.
114 // List of fields/attributes that are constant across all the instruction
119 // Ex: KeyCol = 'noPred' -- key instruction is non-predicated
130 // Each instruction map must specify at least one column for it to be valid
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| /external/google-breakpad/src/processor/ |
| stackwalker_selftest.cc | 165 // The CALL instruction places a 4-byte return address on the stack above
179 // GetEIP returns the instruction pointer identifying the next instruction
181 // stack, where it was placed by the call instruction that called GetEIP.
187 // pointers. Because this function depends on a call instruction and the
220 // GetPC returns the program counter identifying the next instruction to
222 // link register, where it was placed by the branch instruction that called
224 // instruction, inlining is disabled.
273 // GetPC returns the program counter identifying the next instruction to
275 // link register, where it was placed by the branch instruction that calle
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