| /external/llvm/test/MC/Mips/mips5/ |
| invalid-mips32r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/mips64/ |
| invalid-mips32r2.s | 8 di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ei $t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 ei # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/PowerPC/ |
| ppc64-errors.s | 9 # CHECK: error: invalid operand for instruction
19 # CHECK: error: invalid operand for instruction
23 # CHECK: error: invalid operand for instruction
29 # CHECK: error: invalid operand for instruction
33 # CHECK: error: invalid operand for instruction
39 # CHECK: error: invalid operand for instruction
43 # CHECK: error: invalid operand for instruction
49 # CHECK: error: invalid operand for instruction
52 # CHECK: error: invalid operand for instruction
65 # CHECK: error: invalid operand for instruction
[all...] |
| /external/llvm/test/TableGen/ |
| LetInsideMultiClasses.td | 9 class Instruction<bits<4> opc, string Name> {
17 def rr : Instruction<opc, "rr">;
18 def rm : Instruction<opc, "rm">;
22 def rx : Instruction<opc, "rx">;
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| vselect-cost.ll | 14 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
15 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
16 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
17 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
24 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
25 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
26 ; AVX: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
27 ; AVX2: Cost Model: {{.*}} 1 for instruction: %sel = select <2 x i1>
34 ; SSE2: Cost Model: {{.*}} 1 for instruction: %sel = select <4 x i1>
35 ; SSE41: Cost Model: {{.*}} 1 for instruction: %sel = select <4 x i1
[all...] |
| /external/llvm/test/MC/ARM/ |
| pr22395.s | 12 @ CHECK-NOT: error: instruction requires: VFP2
17 @ CHECK-NOT: error: instruction requires: VPF2
22 @ CHECK-NOT: error: instruction requires: VPF2
27 @ CHECK-NOT: error: instruction requires: VPF2
32 @ CHECK-NOT: error: instruction requires: VPF2
37 @ CHECK-NOT: error: instruction requires: VPF2
42 @ CHECK-NOT: error: instruction requires: VPF2
47 @ CHECK-NOT: error: instruction requires: VPF2
52 @ CHECK-NOT: error: instruction requires: VPF2
57 @ CHECK-NOT: error: instruction requires: VPF
[all...] |
| diagnostics-noneon.s | 6 @ CHECK-ERRORS: error: instruction requires: NEON
7 @ CHECK-ERRORS: error: instruction requires: NEON
|
| directive-arch_extension-mode-switch.s | 12 @ CHECK: instruction requires: divide in ARM
16 @ CHECK: instruction requires: divide in THUMB
|
| invalid-idiv.s | 12 @ ARM-A15: error: instruction requires: divide in ARM
14 @ ARM-A15: error: instruction requires: divide in ARM
16 @ THUMB-A15: error: instruction requires: arm-mode
18 @ THUMB-A15: error: instruction requires: arm-mode
21 @ ARM: error: instruction requires: divide in ARM
23 @ ARM: error: instruction requires: divide in ARM
25 @ THUMB: error: instruction requires: divide in THUMB
27 @ THUMB: error: instruction requires: divide in THUMB
|
| ldrd-strd-gnu-arm-bad-imm.s | 3 @ CHECK: error: instruction requires: thumb2
7 @ CHECK: error: instruction requires: thumb2
|
| ldrd-strd-gnu-thumb-bad-regs.s | 4 @ CHECK: error: invalid operand for instruction
8 @ CHECK: error: invalid operand for instruction
|
| udf-arm-diagnostics.s | 10 @ CHECK: error: instruction 'udf' is not predicable, but condition code specified
16 @ CHECK: error: invalid operand for instruction
|
| /art/runtime/ |
| dex_instruction-inl.h | 27 inline bool Instruction::HasVRegA() const {
57 inline int32_t Instruction::VRegA() const {
84 LOG(FATAL) << "Tried to access vA of instruction " << Name() << " which has no A operand.";
89 inline int8_t Instruction::VRegA_10t(uint16_t inst_data) const {
94 inline uint8_t Instruction::VRegA_10x(uint16_t inst_data) const {
99 inline uint4_t Instruction::VRegA_11n(uint16_t inst_data) const {
104 inline uint8_t Instruction::VRegA_11x(uint16_t inst_data) const {
109 inline uint4_t Instruction::VRegA_12x(uint16_t inst_data) const {
114 inline int16_t Instruction::VRegA_20t() const {
119 inline uint8_t Instruction::VRegA_21c(uint16_t inst_data) const
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/program/ |
| MInsn.java | 19 import dexfuzz.rawdex.Instruction;
23 * as the instruction is moved around.
27 * The raw DEX instruction that this instruction represents.
29 public Instruction insn;
33 * The location of this instruction, as an offset in code words from the beginning.
44 * Clone this MInsn, and clone the wrapped Instruction.
56 * Get the String representation of an instruction.
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-armv8.txt | 10 # CHECK: invalid instruction encoding
15 # CHECK: invalid instruction encoding
20 # CHECK: invalid instruction encoding
25 # CHECK: invalid instruction encoding
30 # CHECK: invalid instruction encoding
35 # CHECK: invalid instruction encoding
40 # CHECK: invalid instruction encoding
45 # CHECK: invalid instruction encoding
50 # CHECK: invalid instruction encoding
55 # CHECK: invalid instruction encodin
[all...] |
| invalid-thumbv8.txt | 10 # CHECK: invalid instruction encoding
15 # CHECK: invalid instruction encoding
20 # CHECK: invalid instruction encoding
25 # CHECK: invalid instruction encoding
30 # CHECK: invalid instruction encoding
35 # CHECK: invalid instruction encoding
40 # CHECK: invalid instruction encoding
45 # CHECK: invalid instruction encoding
50 # CHECK: invalid instruction encoding
55 # CHECK: invalid instruction encodin
[all...] |
| unpredictable-BFI.txt | 5 # CHECK: warning: invalid instruction encoding
9 # CHECK: warning: invalid instruction encoding
|
| /external/llvm/test/MC/Disassembler/SystemZ/ |
| trunc-03.txt | 2 # If the top bits are 0b11, the instruction must be 6 bytes long.
3 # CHECK: warning: invalid instruction encoding
|
| /external/llvm/test/MC/Mips/ |
| mips-expansions-bad.s | 6 # CHECK: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
8 # CHECK: :[[@LINE-1]]:3: error: instruction requires a 64-bit architecture
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid-mips32r2.s | 8 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 nmadd.d $f18,$f9,$f14,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 nmsub.d $f30,$f8,$f16,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
15 nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| invalid-mips4.s | 8 bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
9 bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
10 ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
11 lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
12 sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/Mips/msa/ |
| set-msa-directive-bad.s | 5 addvi.b $w14, $w12, 14 # CHECK: error: instruction requires a CPU feature not currently enabled
11 addvi.w $w19, $w13, 11 # CHECK: error: instruction requires a CPU feature not currently enabled
|
| /art/runtime/interpreter/ |
| interpreter_switch_impl.cc | 47 // Code to run before each dex instruction.
78 const Instruction* inst = Instruction::At(insns + dex_pc);
86 case Instruction::NOP:
90 case Instruction::MOVE:
96 case Instruction::MOVE_FROM16:
102 case Instruction::MOVE_16:
108 case Instruction::MOVE_WIDE:
114 case Instruction::MOVE_WIDE_FROM16:
120 case Instruction::MOVE_WIDE_16
[all...] |
| /external/valgrind/none/tests/mips64/ |
| macro_load_store.h | 3 #define TEST1(instruction, offset, mem) \
11 instruction" $t1, 0($t0)" "\n\t" \
18 instruction, offset, out); \
21 #define TEST2(instruction, offset) \
33 instruction" $t3, 0($t1)" "\n\t" \
44 instruction, offset, out, outHI); \
47 #define TEST3(instruction, offset, mem) \
55 instruction" $f0, 0($t0)" "\n\t" \
62 instruction, offset, out); \
65 #define TEST3w(instruction, offset, mem)
[all...] |
| /art/compiler/optimizing/ |
| pretty_printer_test.cc | 45 Instruction::RETURN_VOID);
73 Instruction::GOTO | 0x100,
74 Instruction::RETURN_VOID);
94 Instruction::GOTO | 0x100,
95 Instruction::GOTO | 0x100,
96 Instruction::RETURN_VOID);
116 Instruction::GOTO | 0x200,
117 Instruction::RETURN_VOID,
118 Instruction::GOTO | 0xFF00);
123 Instruction::GOTO_16, 3
[all...] |
