| /external/llvm/test/CodeGen/R600/ |
| lds-oqap-crash.ll | 5 ; if an LDS instruction could fit in the current clause, but never finding
8 ; The LDS instruction should not have been defining OQAP in the first place,
10 ; reads and writes are bundled together in the same instruction.
|
| /external/llvm/test/MC/ARM/ |
| basic-arm-instructions-v8.s | 11 @ CHECK-V7: error: instruction requires: armv8
12 @ CHECK-V7: error: instruction requires: armv8
17 @ CHECK-V7: error: instruction requires: armv8
31 @ CHECK-V7: error: invalid operand for instruction
32 @ CHECK-V7: error: invalid operand for instruction
33 @ CHECK-V7: error: invalid operand for instruction
34 @ CHECK-V7: error: invalid operand for instruction
48 @ CHECK-V7: error: invalid operand for instruction
49 @ CHECK-V7: error: invalid operand for instruction
50 @ CHECK-V7: error: invalid operand for instruction
[all...] |
| /external/llvm/test/MC/Disassembler/SystemZ/ |
| invalid-regs.txt | 5 # CHECK: warning: invalid instruction encoding
12 # CHECK-NEXT: warning: invalid instruction encoding
19 # CHECK-NEXT: warning: invalid instruction encoding
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| invalid.s | 12 ldc2 $8,-21181($at) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
13 sdc2 $20,23157($s2) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
14 swc2 $25,24880($s0) # ASM: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
| /external/llvm/test/MC/X86/AlignedBundling/ |
| pad-align-to-bundle-end.s | 31 # The nop sequence may be implemented as one instruction or many, but if
32 # it's one instruction, that instruction cannot itself cross the boundary.
|
| /external/v8/src/arm64/ |
| instrument-arm64.h | 60 #define DECLARE(A) void Visit##A(Instruction* instr);
74 void InstrumentLoadStore(Instruction* instr);
75 void InstrumentLoadStorePair(Instruction* instr);
|
| /external/valgrind/docs/internals/ |
| MERGE_3_10_1.txt | 6 //339336 PPC64 store quad instruction (stq) is not supposed to
34 //339433 ppc64 lxvw4x instruction uses four 32-byte loads
74 //340036 arm64: Unhandled instruction ld4 (multiple structures, no offset)
88 //339926 Unhandled instruction 0x1E674001 (frintx) on aarm64
92 //339927 Unhandled instruction 0x9E7100C6 (fcvtmu) on aarch64
96 //339938 disInstr(arm64): unhandled instruction 0x4F8010A4 (fmla)
101 //340509 arm64: unhandled instruction fcvtas
105 //335713 arm64: unhanded instruction: prfm (immediate)
109 //340033 arm64: unhandled instruction for dmb ishld and some other
127 //340632 arm64: unhandled instruction fcvta
[all...] |
| /external/valgrind/none/tests/s390x/ |
| op00.stderr.exp1 | 3 valgrind: Unrecognised instruction at address 0x.........
5 Your program just tried to execute an instruction that Valgrind
10 2. The instruction is legitimate but Valgrind doesn't handle it,
|
| op00.stderr.exp2 | 3 valgrind: Unrecognised instruction at address 0x.........
5 Your program just tried to execute an instruction that Valgrind
10 2. The instruction is legitimate but Valgrind doesn't handle it,
|
| op_exception.stderr.exp | 3 valgrind: Unrecognised instruction at address 0x.........
5 Your program just tried to execute an instruction that Valgrind
10 2. The instruction is legitimate but Valgrind doesn't handle it,
16 valgrind: Unrecognised instruction at address 0x.........
18 Your program just tried to execute an instruction that Valgrind
23 2. The instruction is legitimate but Valgrind doesn't handle it,
29 valgrind: Unrecognised instruction at address 0x.........
31 Your program just tried to execute an instruction that Valgrind
36 2. The instruction is legitimate but Valgrind doesn't handle it,
42 valgrind: Unrecognised instruction at address 0x........
[all...] |
| /external/proguard/lib/ |
| proguard.jar | |
| /art/tools/dexfuzz/src/dexfuzz/program/ |
| MutatableCode.java | 20 import dexfuzz.rawdex.Instruction;
168 * Checks if any MTryBlock's instruction refs pointed at the 'before' MInsn,
179 Log.debug("Try block's first instruction was updated");
182 Log.debug("Try block's first instruction was updated");
186 Log.debug("Try block's last instruction was updated");
189 Log.debug("Try block's last instruction was updated");
193 Log.debug("Try block's catch-all instruction was updated");
196 Log.debug("Try block's catch-all instruction was updated");
210 Log.debug("Try block's handler instruction was updated");
213 Log.debug("Try block's handler instruction was updated")
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.h | 1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
76 /// \returns true if this \p Opcode represents an ALU instruction.
83 /// \returns true if this \p Opcode represents an ALU instruction or an
84 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
107 /// of the instruction's src operands.
132 /// starting from the one already provided in the Instruction Group MIs that
137 /// apply to the last instruction.
138 /// PV holds GPR to PV registers in the Instruction Group MIs.
144 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
152 /// instruction slots within an instruction group
[all...] |
| /external/valgrind/none/tests/mips32/ |
| fpu_branches.c | 42 #define TESTINST1s(instruction, RDval) \
50 instruction" end"instruction"s"#RDval "\n\t" \
53 "end"instruction"s"#RDval":" "\n\t" \
61 instruction, outf, fs_f[i], ft_f[i]); \
64 #define TESTINST1d(instruction, RDval) \
72 instruction" end"instruction"d"#RDval "\n\t" \
75 "end"instruction"d"#RDval":" "\n\t" \
83 instruction, outd, fs_d[i], ft_d[i]);
[all...] |
| /art/compiler/optimizing/ |
| ssa_liveness_analysis.h | 55 * A live range contains the start and end of a range where an instruction or a temporary
172 explicit SafepointPosition(HInstruction* instruction)
173 : instruction_(instruction),
204 * An interval is a list of disjoint live ranges where an instruction is live.
205 * Each instruction that has uses gets an interval.
211 HInstruction* instruction = nullptr) {
212 return new (allocator) LiveInterval(allocator, type, instruction);
215 static LiveInterval* MakeSlowPathInterval(ArenaAllocator* allocator, HInstruction* instruction) {
217 allocator, Primitive::kPrimVoid, instruction, false, kNoRegister, false, true);
234 void AddTempUse(HInstruction* instruction, size_t temp_index)
1128 HInstruction* instruction = GetInstructionFromPosition(index); local
[all...] |
| /external/v8/src/mips/ |
| disasm-mips.cc | 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be
60 // Writes one disassembled instruction into 'buffer' (0-terminated).
61 // Returns the length of the disassembled machine instruction in bytes.
62 int InstructionDecode(byte* instruction);
72 void PrintRs(Instruction* instr);
73 void PrintRt(Instruction* instr);
74 void PrintRd(Instruction* instr);
75 void PrintFs(Instruction* instr);
76 void PrintFt(Instruction* instr)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 45 /// MachineInstr - Representation of each machine instruction.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
76 unsigned NumOperands; // Number of operands on instruction.
82 // instruction.
209 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
215 /// isBundled - Return true if this instruction part of a bundle. This is true
216 /// if either itself or its following instruction is marked "InsideBundle"
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| OutputFinisher.java | 34 * Processor for instruction lists, which takes a "first cut" of
35 * instruction selection as a basis and produces a "final cut" in the
48 /** whether any instruction has position info */
51 /** whether any instruction has local variable info */
99 * instruction for local variable information.
101 * @param insn {@code non-null;} instruction to scrutinize
102 * @return {@code true} iff the instruction refers to any
155 * a single instruction.
158 * @param insn {@code non-null;} instruction to scrutinize
209 * Adds an instruction to the output
[all...] |
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputFinisher.java | 39 * Processor for instruction lists, which takes a "first cut" of
40 * instruction selection as a basis and produces a "final cut" in the
56 /** whether any instruction has position info */
59 /** whether any instruction has local variable info */
121 * instruction for local variable information.
123 * @param insn {@code non-null;} instruction to scrutinize
124 * @return {@code true} iff the instruction refers to any
177 * a single instruction.
180 * @param insn {@code non-null;} instruction to scrutinize
231 * Adds an instruction to the output
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyIndVar.cpp | 70 Value *foldIVUser(Instruction *UseInst, Instruction *IVOperand);
72 bool eliminateIVUser(Instruction *UseInst, Instruction *IVOperand);
78 Instruction *splitOverflowIntrinsic(Instruction *IVUser,
84 /// aligned IV when used by a instruction that ignores the low bits.
91 Value *SimplifyIndvar::foldIVUser(Instruction *UseInst, Instruction *IVOperand) {
98 case Instruction::UDiv
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.mli | 51 (** The kind id of metadata attached to an instruction. *)
165 (** The predicate for an integer comparison ([icmp]) instruction.
181 (** The predicate for a floating-point comparison ([fcmp]) instruction.
208 | Invalid (** Not an instruction *)
276 (** The type of a clause of a [landingpad] instruction.
297 [fence] instruction. See [llvm::AtomicOrdering]. *)
310 (** The opcode of an [atomicrmw] instruction.
352 | Instruction of Opcode.t
792 (** [has_metadata i] returns whether or not the instruction [i] has any
794 [llvm::Instruction::hasMetadata]. *
[all...] |
| /dalvik/docs/ |
| java-constraints.html | 142 The index of instruction <code>n+1</code> must equal the index of
143 instruction <code>n</code> plus the length of instruction
145 instruction. Opcodes modified by a <code>wide</code> instruction must
164 The last instruction in <code>code</code> array must end at index
184 Opcodes modified by a <code>wide</code> instruction must not be
185 directly reachable via a jump or branch instruction.
203 All targets of a <code>tableswitch</code> instruction must be opcodes
205 Opcodes modified by a <code>wide</code> instruction must not b
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/dex/code/ |
| OutputFinisher.java | 38 * Processor for instruction lists, which takes a "first cut" of
39 * instruction selection as a basis and produces a "final cut" in the
55 /** whether any instruction has position info */
58 /** whether any instruction has local variable info */
108 * instruction for local variable information.
110 * @param insn {@code non-null;} instruction to scrutinize
111 * @return {@code true} iff the instruction refers to any
164 * a single instruction.
167 * @param insn {@code non-null;} instruction to scrutinize
218 * Adds an instruction to the output
[all...] |
| /external/lldb/scripts/Python/interface/ |
| SBInstructionList.i | 18 SBInstructionList supports instruction (SBInstruction instance) iteration.
64 '''Access len of the instruction list.'''
68 '''Access instructions by integer index for array access or by lldb.SBAddress to find an instruction that matches a section offset address object.'''
70 # Find an instruction by index
74 # Find an instruction using a lldb.SBAddress object
|
| /external/llvm/include/llvm/IR/ |
| AssemblyAnnotationWriter.h | 24 class Instruction;
39 /// after the basic block label, but before the first instruction in the
52 /// before an instruction is emitted.
53 virtual void emitInstructionAnnot(const Instruction *,
57 /// right of an instruction or global value.
|
