| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DbgValueHistoryCalculator.h | 24 // For each user variable, keep a list of instruction ranges where this variable
27 // Each instruction range starts with a DBG_VALUE instruction, specifying the
30 // instruction of the next instruction range, or until the end of the
|
| /external/llvm/test/CodeGen/R600/ |
| structurize.ll | 19 ; === Branch instruction (IF):
28 ; === Branch instruction (ELSE):
32 ; === Branch instruction (IF):
36 ; === Branch instruction (ELSE):
40 ; === Branch instruction (ENDIF):
|
| /external/llvm/test/ExecutionEngine/RuntimeDyld/AArch64/ |
| MachO_ARM64_relocations.s | 16 # Test ARM64_RELOC_BRANCH26 relocation. The branch instruction only encodes 26
27 # the PC-relative page (4 KiB) difference between the adrp instruction and the
29 # instruction perfroms an implicit shift on the encoded immediate (imm<<3).
43 # adrp instruction and the GOT entry for ptr. ldr encodes the offset of the GOT
44 # entry within the page. The ldr instruction perfroms an implicit shift on the
|
| /external/llvm/test/MC/ARM/ |
| directive-arch_extension-mp.s | 24 @ CHECK-V6: error: instruction requires: mp-extensions armv7
25 @ CHECK-V7M: error: instruction requires: mp-extensions
35 @ CHECK-V6: error: instruction requires: mp-extensions armv7
36 @ CHECK-V7: error: instruction requires: mp-extensions
37 @ CHECK-V7M: error: instruction requires: mp-extensions
|
| /external/llvm/test/TableGen/ |
| BitOffsetDecoder.td | 18 def foo : Instruction {
28 def bar : Instruction {
38 def biz : Instruction {
48 def baz : Instruction {
58 def bum : Instruction {
|
| /external/llvm/utils/TableGen/ |
| X86DisassemblerTables.h | 50 /// The instruction information table
53 /// True if there are primary decode conflicts in the instruction set
153 /// emitInstructionInfo - Prints the instruction specifier table, which has
154 /// one entry for each instruction, and contains name and operand
173 /// nnnn is the ID of the current instruction (0-based). This table
175 /// 0xnn is the lowest possible opcode for the current instruction, used for
179 /// @param o - The output stream to which the instruction table should be
185 /// instruction attribute mask to an instruction context. This table is
214 /// ModRMDecision to refer to a particular instruction ID
[all...] |
| /external/proguard/src/proguard/classfile/visitor/ |
| DotClassClassVisitor.java | 27 import proguard.classfile.instruction.*;
28 import proguard.classfile.instruction.visitor.InstructionVisitor;
62 public void visitAnyInstruction(Clazz clazz, Method method, CodeAttribute codeAttribute, int offset, Instruction instruction) {}
69 // Could this instruction be a .class construct?
|
| /external/proguard/src/proguard/optimize/peephole/ |
| PeepholeOptimizer.java | 27 import proguard.classfile.instruction.visitor.InstructionVisitor;
32 * instruction visitor. The instruction visitor should be using the same
50 * @param instructionVisitor the instruction visitor that performs
67 * @param instructionVisitor the instruction visitor that performs
|
| /external/smali/baksmali/src/main/java/org/jf/baksmali/Adaptors/Format/ |
| OffsetInstructionFormatMethodItem.java | 35 import org.jf.dexlib2.iface.instruction.OffsetInstruction;
45 int codeAddress, OffsetInstruction instruction) {
46 super(methodDef, codeAddress, instruction);
48 label = new LabelMethodItem(options, codeAddress + instruction.getCodeOffset(), getLabelPrefix());
62 Opcode opcode = instruction.getOpcode();
|
| /external/apache-xml/src/main/java/org/apache/xalan/templates/ |
| ElemPI.java | 31 * Implement xsl:processing-instruction.
33 * <!ELEMENT xsl:processing-instruction %char-template;>
34 * <!ATTLIST xsl:processing-instruction
47 * The xsl:processing-instruction element has a required name
48 * attribute that specifies the name of the processing instruction node.
115 * Create a processing instruction in the result tree.
116 * The content of the xsl:processing-instruction element is a
117 * template for the string-value of the processing instruction node.
134 // Ignore processing instruction if name is null
146 // Ignore processing instruction, if invali
[all...] |
| /external/google-breakpad/src/processor/ |
| stackwalker_ppc.cc | 73 // The instruction pointer is stored directly in a register, so pull it
78 frame->instruction = frame->context.srr0;
91 // The instruction pointers for previous frames are saved on the stack.
118 uint32_t instruction; local
119 if (!memory_->GetMemoryAtAddress(stack_pointer + 8, &instruction) ||
120 instruction <= 1) {
127 frame->context.srr0 = instruction;
133 // frame->context.srr0 is the return address, which is one instruction
135 // frame_ppc->instruction to four less than that. Since all ppc
137 // instruction. This allows source line information to match up with th
[all...] |
| stackwalker_ppc64.cc | 64 // The instruction pointer is stored directly in a register, so pull it
69 frame->instruction = frame->context.srr0;
82 // The instruction pointers for previous frames are saved on the stack.
109 uint64_t instruction; local
110 if (!memory_->GetMemoryAtAddress(stack_pointer + 16, &instruction) ||
111 instruction <= 1) {
118 frame->context.srr0 = instruction;
124 // frame->context.srr0 is the return address, which is one instruction
126 // frame_ppc64->instruction to eight less than that. Since all ppc64
128 // instruction. This allows source line information to match up with th
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| PHITransAddr.h | 18 #include "llvm/IR/Instruction.h"
50 SmallVector<Instruction*, 4> InstInputs;
54 // If the address is an instruction, the whole thing is considered an input.
55 if (Instruction *I = dyn_cast<Instruction>(Addr))
93 SmallVectorImpl<Instruction*> &NewInsts);
112 SmallVectorImpl<Instruction*> &NewInsts);
114 /// AddAsInput - If the specified value is an instruction, add it as an input.
116 // If V is an instruction, it is now an input.
117 if (Instruction *VI = dyn_cast<Instruction>(V)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| DFAPacketizer.h | 16 // the packetizing mechanism, the input is the set of instruction classes for
19 // models the addition of an instruction to a packet. In the DFA constructed
20 // by this class, if an instruction can be added to a packet, then a valid
22 // indicate that the instruction cannot be added to the current packet.
75 // instruction are available in the current state.
79 // instruction and change the current state to reflect that change.
86 // packetizer works on machine basic blocks. For each instruction I in BB, the
88 // execute I. If so, the packetizer checks if I depends on any instruction J in
133 // an instruction. This function is supposed to be overrided by
143 // isSoloInstruction - return true if instruction MI can not be packetize
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| DCE.cpp | 22 #include "llvm/IR/Instruction.h"
49 Instruction *Inst = DI++;
67 "Dead Instruction Elimination", false, false)
103 std::vector<Instruction*> WorkList;
113 Instruction *I = WorkList.back();
116 if (isInstructionTriviallyDead(I, TLI)) { // If the instruction is dead.
117 // Loop over all of the values that the instruction uses, if there are
122 if (Instruction *Used = dyn_cast<Instruction>(*OI))
125 // Remove the instruction
[all...] |
| LICM.cpp | 20 // we can hoist it or sink it like any other instruction.
21 // 2. Scalar Promotion of Memory - If there is a store instruction inside of
75 static bool isNotUsedInLoop(Instruction &I, Loop *CurLoop);
76 static bool hoist(Instruction &I, BasicBlock *Preheader);
77 static bool sink(Instruction &I, LoopInfo *LI, DominatorTree *DT,
79 static bool isGuaranteedToExecute(Instruction &Inst, DominatorTree *DT,
81 static bool isSafeToExecuteUnconditionally(Instruction &Inst, DominatorTree *DT,
87 static Instruction *CloneInstructionInExitBlock(Instruction &I,
90 static bool canSinkOrHoistInst(Instruction &I, AliasAnalysis *AA
[all...] |
| /external/llvm/test/Transforms/LoopVectorize/ARM/ |
| mul-cast-vect.ll | 24 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
39 ; COST: cost of 0 for instruction: {{.*}} sext <4 x i16> {{.*}} to <4 x i32>
41 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
56 ; COST: cost of 0 for instruction: {{.*}} zext <4 x i16> {{.*}} to <4 x i32>
58 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32>
73 ; COST: cost of 1 for instruction: {{.*}} mul <2 x i32>
76 ; COST: cost of 1 for instruction: {{.*}} sext <2 x i32> {{.*}} to <2 x i64>
90 ; COST: cost of 1 for instruction: {{.*}} mul <2 x i32>
93 ; COST: cost of 1 for instruction: {{.*}} zext <2 x i32> {{.*}} to <2 x i64>
107 ; COST: cost of 2 for instruction: {{.*}} mul <4 x i32
[all...] |
| /external/mockito/cglib-and-asm/src/org/mockito/asm/ |
| MethodVisitor.java | 106 * instruction <b>i</b> that follows an unconditionnal branch instruction
107 * such as GOTO or THROW, that is the target of a jump instruction, or that
145 * types by Label objects (this label designates the NEW instruction
163 * Visits a zero operand instruction.
165 * @param opcode the opcode of the instruction to be visited. This opcode is
183 * Visits an instruction with a single int operand.
185 * @param opcode the opcode of the instruction to be visited. This opcode is
187 * @param operand the operand of the instruction to be visited.<br> When
200 * Visits a local variable instruction. A local variable instruction is an
[all...] |
| /external/v8/src/compiler/ |
| code-generator.h | 11 #include "src/compiler/instruction.h"
52 // Assemble code for the specified instruction.
53 void AssembleInstruction(Instruction* instr);
61 void AssembleArchInstruction(Instruction* instr);
62 void AssembleArchBranch(Instruction* instr, FlagsCondition condition);
63 void AssembleArchBoolean(Instruction* instr, FlagsCondition condition);
86 void AddSafepointAndDeopt(Instruction* instr);
89 FrameStateDescriptor* GetFrameStateDescriptor(Instruction* instr,
91 int BuildTranslation(Instruction* instr, int pc_offset,
95 FrameStateDescriptor* descriptor, Instruction* instr
[all...] |
| /external/vixl/examples/ |
| custom-disassembler.cc | 37 const Instruction* instr,
86 const Instruction* instr, const void* addr) {
105 // We override this method to add a comment to this type of instruction. Helpers
106 // from the vixl::Instruction class can be used to analyse the instruction being
108 void CustomDisassembler::VisitAddSubShifted(const Instruction* instr) {
148 Instruction* instr_start = masm.GetLabelAddress<Instruction*>(&code_start);
149 Instruction* instr_end = masm.GetLabelAddress<Instruction*>(&code_end)
[all...] |
| /external/lldb/scripts/Python/interface/ |
| SBInstruction.i | 82 if _newclass: mnemonic = property(__mnemonic_property__, None, doc='''A read only property that returns the mnemonic for this instruction as a string.''')
85 if _newclass: operands = property(__operands_property__, None, doc='''A read only property that returns the operands for this instruction as a string.''')
88 if _newclass: comment = property(__comment_property__, None, doc='''A read only property that returns the comment for this instruction as a string.''')
91 if _newclass: addr = property(GetAddress, None, doc='''A read only property that returns an lldb object that represents the address (lldb.SBAddress) for this instruction.''')
94 if _newclass: size = property(GetByteSize, None, doc='''A read only property that returns the size in bytes for this instruction as an integer.''')
97 if _newclass: is_branch = property(DoesBranch, None, doc='''A read only property that returns a boolean value that indicates if this instruction is a branch instruction.''')
|
| /external/llvm/docs/HistoricalNotes/ |
| 2000-11-18-EarlyDesignIdeas.txt | 41 -- an instruction to say "I speculate that these two values are not
44 -- or an instruction to check whether two values are aliased and
49 A "thread-id" field on every instruction that allows the static
52 This has very powerful uses, but thread-id on every instruction
53 is expensive in terms of instruction size and code size.
61 o Or forget all this and stick to a traditional instruction set?
65 that you had suggested doing instruction scheduling on SSA form instead
|
| /external/llvm/include/llvm/IR/ |
| AutoUpgrade.h | 23 class Instruction;
49 /// If the TBAA tag for the given instruction uses the scalar TBAA format,
51 void UpgradeInstWithTBAATag(Instruction *I);
54 /// address spaces: the instruction is replaced by a pair ptrtoint+inttoptr.
55 Instruction *UpgradeBitCastInst(unsigned Opc, Value *V, Type *DestTy,
56 Instruction *&Temp);
59 /// with different address spaces: the instruction is replaced by a pair
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsAsmBackend.h | 53 /// MayNeedRelaxation - Check whether the given instruction may need
56 /// \param Inst - The instruction to test.
62 /// fixup requires the associated instruction to be relaxed.
71 /// RelaxInstruction - Relax the instruction in the given fragment
72 /// to the next wider instruction.
74 /// \param Inst - The instruction to relax, which may be the same
76 /// \param [out] Res On return, the relaxed instruction.
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.h | 85 /// \brief Emit the COPY_FW pseudo instruction
88 /// \brief Emit the COPY_FD pseudo instruction
91 /// \brief Emit the INSERT_FW pseudo instruction
94 /// \brief Emit the INSERT_FD pseudo instruction
97 /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction
102 /// \brief Emit the FILL_FW pseudo instruction
105 /// \brief Emit the FILL_FD pseudo instruction
|
