| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 1 //===-- SparcInstrInfo.h - Sparc Instruction Information --------*- C++ -*-===//
28 /// instruction info tracks.
47 /// such, whenever a client has an instance of instruction info, it should
52 /// isLoadFromStackSlot - If the specified machine instruction is a direct
55 /// not, return 0. This predicate must return 0 if the instruction has
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 /// not, return 0. This predicate must return 0 if the instruction has
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
32 /// such, whenever a client has an instance of instruction info, it should
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
40 /// not, return 0. This predicate must return 0 if the instruction has
45 /// isStoreToStackSlot - If the specified machine instruction is a direct
48 /// not, return 0. This predicate must return 0 if the instruction has
86 // Returns an iterator to the new instruction.
|
| /external/llvm/test/MC/ARM/ |
| thumb-hints.s | 36 @ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
39 @ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
42 @ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
45 @ CHECK-ERROR: error: instruction requires: armv6m or armv6t2
51 @ CHECK-ERROR: error: instruction requires: data-barriers
57 @ CHECK-ERROR: error: instruction requires: data-barriers
63 @ CHECK-ERROR: error: instruction requires: data-barriers
|
| thumbv7m.s | 7 @ These tests test instruction encodings specific to ARMv7m.
33 @ CHECK-V6M: error: invalid operand for instruction
35 @ CHECK-V6M: error: invalid operand for instruction
37 @ CHECK-V6M: error: invalid operand for instruction
39 @ CHECK-V6M: error: invalid operand for instruction
41 @ CHECK-V6M: error: invalid operand for instruction
43 @ CHECK-V6M: error: invalid operand for instruction
|
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_build_util.cpp | 65 Instruction *
68 Instruction *insn = new_Instruction(func, op, ty);
77 Instruction *
81 Instruction *insn = new_Instruction(func, op, ty);
91 Instruction *
95 Instruction *insn = new_Instruction(func, op, ty);
109 Instruction *insn = new_Instruction(func, OP_LOAD, ty);
121 Instruction *
125 Instruction *insn = new_Instruction(func, op, ty);
136 Instruction *
[all...] |
| /external/proguard/src/proguard/optimize/info/ |
| SideEffectMethodMarker.java | 26 import proguard.classfile.instruction.*;
143 // Get the current instruction.
144 Instruction instruction = InstructionFactory.create(code, offset); local
151 instruction))
156 // Go to the next instruction.
157 offset += instruction.length(offset);
|
| /external/proguard/src/proguard/optimize/peephole/ |
| UnreachableExceptionRemover.java | 26 import proguard.classfile.instruction.*;
119 // Get the current instruction.
120 Instruction instruction = InstructionFactory.create(code, offset); local
123 if (instruction.mayThrowExceptions())
128 // Go to the next instruction.
129 offset += instruction.length(offset);
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
| ImmutableArrayPayload.java | 32 package org.jf.dexlib2.immutable.instruction;
37 import org.jf.dexlib2.iface.instruction.formats.ArrayPayload;
67 public static ImmutableArrayPayload of(ArrayPayload instruction) {
68 if (instruction instanceof ImmutableArrayPayload) {
69 return (ImmutableArrayPayload)instruction;
72 instruction.getElementWidth(),
73 instruction.getArrayElements());
|
| /external/v8/src/mips64/ |
| simulator-mips64.h | 188 // instruction.
268 void Format(Instruction* instr, const char* format);
276 inline uint16_t ReadHU(int64_t addr, Instruction* instr);
277 inline int16_t ReadH(int64_t addr, Instruction* instr);
279 inline void WriteH(int64_t addr, uint16_t value, Instruction* instr);
280 inline void WriteH(int64_t addr, int16_t value, Instruction* instr);
282 inline uint32_t ReadWU(int64_t addr, Instruction* instr);
283 inline int32_t ReadW(int64_t addr, Instruction* instr);
284 inline void WriteW(int64_t addr, int32_t value, Instruction* instr);
285 inline int64_t Read2W(int64_t addr, Instruction* instr)
[all...] |
| /art/compiler/optimizing/ |
| constant_folding_test.cc | 89 Instruction::CONST_4 | 0 << 8 | 1 << 12,
90 Instruction::NEG_INT | 1 << 8 | 0 << 12,
91 Instruction::RETURN | 1 << 8);
147 Instruction::CONST_4 | 0 << 8 | 1 << 12,
148 Instruction::CONST_4 | 1 << 8 | 2 << 12,
149 Instruction::ADD_INT | 2 << 8, 0 | 1 << 8,
150 Instruction::RETURN | 2 << 8);
213 Instruction::CONST_4 | 0 << 8 | 1 << 12,
214 Instruction::CONST_4 | 1 << 8 | 2 << 12,
215 Instruction::ADD_INT_2ADDR | 0 << 8 | 1 << 12
[all...] |
| primitive_type_propagation.cc | 40 // Re-compute and update the type of the instruction. Returns
112 HPhi* instruction = worklist_.Pop(); local
113 if (UpdateType(instruction)) {
114 AddDependentInstructionsToWorklist(instruction);
119 void PrimitiveTypePropagation::AddToWorklist(HPhi* instruction) {
120 DCHECK(instruction->IsLive());
121 worklist_.Add(instruction);
124 void PrimitiveTypePropagation::AddDependentInstructionsToWorklist(HInstruction* instruction) {
125 for (HUseIterator<HInstruction*> it(instruction->GetUses()); !it.Done(); it.Advance()) {
127 if (phi != nullptr && phi->IsLive() && phi->GetType() != instruction->GetType())
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 1 //===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
10 // This file describes the target machine instruction set to the code generator.
50 /// TargetInstrInfo - Interface to description of machine instruction set
63 /// getRegClass - Givem a machine instruction descriptor, returns the register
70 /// isTriviallyReMaterializable - Return true if the instruction is trivially
84 /// specify whether the instruction is actually trivially rematerializable,
86 /// if the instruction has any side effects other than producing a value, or
97 /// target-independent tests to determine if the instruction is really
112 /// Returns the actual stack pointer adjustment made by an instruction
118 /// isCoalescableExtInstr - Return true if the instruction is a "coalescable
[all...] |
| TargetItinerary.td | 11 // which should be implemented by each target that uses instruction
13 // tables for each instruction class. They are most appropriate for
23 // during scheduling and has an affect instruction order based on availability
43 // Instruction stage - These values represent a non-pipelined step in
44 // the execution of an instruction. Cycles represents the number of
67 // Instruction itinerary - An itinerary represents a sequential series of steps
68 // required to complete an instruction. Itineraries are represented as lists of
69 // instruction stages.
73 // Instruction itinerary classes - These values represent 'named' instruction
[all...] |
| Target.td | 117 // require larger instruction encodings.
175 // meaning it takes a single instruction to perform the copying. A negative
192 // model instruction operand constraints, and should have isAllocatable = 0.
321 // Instruction set description - These classes correspond to the C++ classes in
324 class Instruction {
329 string AsmString = ""; // The .s format to print the instruction with.
331 // Pattern - Set to the DAG pattern for this instruction, if we know of one,
336 // instruction pattern.
345 // Size - Size of encoded instruction, or zero if the size cannot be determined
349 // DecoderNamespace - The "namespace" in which this instruction exists, o
[all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_lowering_nvc0.cpp | 49 void handleDIV(Instruction *); // integer division, modulus
50 void handleRCPRSQ(Instruction *); // double precision float recip/rsqrt
57 NVC0LegalizeSSA::handleDIV(Instruction *i)
84 NVC0LegalizeSSA::handleRCPRSQ(Instruction *i)
99 Instruction *next;
100 for (Instruction *i = bb->getEntry(); i; i = next) {
130 void replaceZero(Instruction *);
131 void split64BitOp(Instruction *);
137 TexUse(Instruction *use, const Instruction *tex
[all...] |
| /external/llvm/lib/Target/CppBackend/ |
| CPPBackend.cpp | 24 #include "llvm/IR/Instruction.h"
163 void printInstruction(const Instruction *I, const std::string& bbname);
828 if (CE->getOpcode() == Instruction::GetElementPtr) {
847 case Instruction::Trunc: Out << "Instruction::Trunc"; break;
848 case Instruction::ZExt: Out << "Instruction::ZExt"; break;
849 case Instruction::SExt: Out << "Instruction::SExt"; break;
850 case Instruction::FPTrunc: Out << "Instruction::FPTrunc"; break
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | 46 if (I->getOpcode() == Instruction::Shl) {
53 if (I->getOpcode() == Instruction::Mul) {
60 if (I->getOpcode() == Instruction::Add) {
79 /// PromoteCastOfAllocation - If we find a cast of an allocation instruction,
81 Instruction *InstCombiner::PromoteCastOfAllocation(BitCastInst &CI,
149 // New is the allocation instruction, pointer typed. AI is the original
150 // allocation instruction, also pointer typed. Thus, cast to use is BitCast.
170 // Otherwise, it must be an instruction.
171 Instruction *I = cast<Instruction>(V)
[all...] |
| /art/compiler/dex/quick/mips/ |
| int_mips.cc | 465 bool MipsMir2Lir::SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div,
532 void MipsMir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
536 case Instruction::NOT_LONG:
539 case Instruction::ADD_LONG:
540 case Instruction::ADD_LONG_2ADDR:
543 case Instruction::SUB_LONG:
544 case Instruction::SUB_LONG_2ADDR:
547 case Instruction::MUL_LONG:
548 case Instruction::MUL_LONG_2ADDR:
551 case Instruction::DIV_LONG
[all...] |
| /external/vixl/src/vixl/a64/ |
| instructions-a64.cc | 74 bool Instruction::IsLoad() const {
104 bool Instruction::IsStore() const {
132 uint64_t Instruction::ImmLogical() const {
183 uint32_t Instruction::ImmNEONabcdefgh() const {
188 float Instruction::Imm8ToFP32(uint32_t imm8) {
202 float Instruction::ImmFP32() const {
207 double Instruction::Imm8ToFP64(uint32_t imm8) {
222 double Instruction::ImmFP64() const {
227 float Instruction::ImmNEONFP32() const {
232 double Instruction::ImmNEONFP64() const
[all...] |
| /external/llvm/docs/ |
| HowToUseInstrMappings.rst | 2 How To Use Instruction Mappings
11 This document contains information about adding instruction mapping support
13 between different instruction formats during various optimizations. One approach
16 because of the hardcoded instruction names. Also, whenever a new instruction is
50 // the key instruction. This is the instruction that will be transformed
56 // instruction will be transformed into.
65 takes a non-predicated instruction and returns its predicated true or false form
70 instruction since they are the one used to query the interface function
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| ScalarEvolutionExpander.h | 45 std::map<std::pair<const SCEV *, Instruction *>, TrackingVH<Value> >
56 /// returns the add instruction that adds one to the phi for {0,+,1}<L>,
67 Instruction *IVIncInsertPos;
132 Instruction *getIVIncOperand(Instruction *IncV, Instruction *InsertPos,
136 bool hoistIVInc(Instruction *IncV, Instruction *InsertPos);
147 Value *expandCodeFor(const SCEV *SH, Type *Ty, Instruction *I);
150 void setIVIncInsertPos(const Loop *L, Instruction *Pos)
[all...] |
| /art/runtime/quick/ |
| inline_method_analyser.h | 162 static constexpr bool IsInstructionIGet(Instruction::Code opcode) {
163 return Instruction::IGET <= opcode && opcode <= Instruction::IGET_SHORT;
166 static constexpr bool IsInstructionIPut(Instruction::Code opcode) {
167 return Instruction::IPUT <= opcode && opcode <= Instruction::IPUT_SHORT;
170 static constexpr uint16_t IGetVariant(Instruction::Code opcode) {
171 return opcode - Instruction::IGET;
174 static constexpr uint16_t IPutVariant(Instruction::Code opcode) {
175 return opcode - Instruction::IPUT
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 109 * An if instruction can become an if-*z instruction.
125 * An instruction can be commuted to a literal operation
139 * Tries to replace an instruction with a const instruction. The given
140 * instruction must have a constant result for it to be replaced.
142 * @param insn {@code non-null;} instruction to try to replace
143 * @return true if the instruction was replaced
154 // Replace the instruction with a constant
183 * @param cst {@code null-ok;} constant for new instruction, if an
[all...] |
| /dalvik/libdex/ |
| InstrUtils.h | 18 * Dalvik instruction utility functions.
27 * Possible instruction formats associated with Dalvik opcodes.
30 * opcodes and instruction formats.
84 * Instruction width implied by an opcode's format; a value in the
127 * Holds the contents of a decoded instruction.
140 * Return the instruction width of the specified opcode, or 0 if not defined.
149 * Return the width of the specified instruction, or 0 if not defined. Also
173 * Return the instruction format for the specified opcode.
182 * Return the instruction index type for the specified opcode.
191 * Decode the instruction pointed to by "insns"
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 110 * An if instruction can become an if-*z instruction.
126 * An instruction can be commuted to a literal operation
140 * Tries to replace an instruction with a const instruction. The given
141 * instruction must have a constant result for it to be replaced.
143 * @param insn {@code non-null;} instruction to try to replace
144 * @return true if the instruction was replaced
155 // Replace the instruction with a constant
184 * @param cst {@code null-ok;} constant for new instruction, if an
[all...] |
