| /external/vixl/src/vixl/a64/ |
| instructions-a64.h | 44 // This is the nominal page size (as used by the adrp instruction); the actual
151 // the instruction (such as with fcvta). It cannot be set in FPCR.
163 class Instruction {
286 // does not check that the instruction actually has an Rd field.
315 // does not check that the instruction actually has an Rn field.
342 // Find the target of this instruction. 'this' may be a branch or a
343 // PC-relative addressing instruction.
344 const Instruction* ImmPCOffsetTarget() const;
347 // a PC-relative addressing instruction.
348 void SetImmPCOffsetTarget(const Instruction* target)
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| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
78 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
103 /// MTCTR instruction.
107 /// BCTRL instruction.
111 /// instruction and the TOC reload required on SVR4 PPC64.
117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
160 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
198 /// TLS model, produces an ADDIS8 instruction that adds the GO
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| /external/llvm/include/llvm/CodeGen/ |
| MachineTraceMetrics.h | 41 // Every instruction in the current block has a slack - the number of cycles
42 // execution of the instruction can be delayed without extending the critical
123 /// For virtual registers: Minimum height of the defining instruction.
176 /// useful instruction depths. A dominating block can be above the current
185 // Instruction depths are only comparable if the traces share a head.
192 // increase the instruction depth.
196 // Data-dependency-related information. Per-instruction depth and height
200 /// Instruction depths have been computed. This implies hasValidDepth().
203 /// Instruction heights have been computed. This implies hasValidHeight().
220 /// InstrCycles represents the cycle height and depth of an instruction in
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| SlotIndexes.h | 112 /// the same instruction (Slot_Register or Slot_EarlyClobber), but isn't
205 /// isSameInstr - Return true if A and B refer to the same instruction.
210 /// isEarlierInstr - Return true if A refers to an instruction earlier than
222 /// slots on the same instruction have zero distance.
242 /// is the one associated with the Slot_Block slot for the instruction
249 /// index is the one associated with the Slot_Block slot for the instruction
255 /// Returns the register use/def slot in the current instruction for a
261 /// Returns the dead def kill slot for the current instruction.
267 /// next slot for the instruction pointed to by this index or, if this
268 /// index is a STORE, the first slot for the next instruction
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| /external/llvm/include/llvm/Transforms/Utils/ |
| Local.h | 29 class Instruction;
51 /// ConstantFoldTerminator - If a terminator instruction is predicated on a
66 /// instruction is not used, and the instruction has no side effects.
68 bool isInstructionTriviallyDead(Instruction *I,
72 /// trivially dead instruction, delete it. If that makes any of its operands
80 /// either forms a cycle or is terminated by a trivially dead instruction,
154 /// Instruction and replaces it with a slot in the stack frame, allocated via
159 AllocaInst *DemoteRegToStack(Instruction &X,
161 Instruction *AllocaPoint = nullptr)
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| /external/llvm/lib/Target/R600/ |
| AMDGPUPromoteAlloca.cpp | 86 Instruction *Use = dyn_cast<Instruction>(*U);
133 // Not an instruction handled below to turn into a vector.
137 static bool canVectorizeInst(Instruction *Inst) {
139 case Instruction::Load:
140 case Instruction::Store:
141 case Instruction::BitCast:
142 case Instruction::AddrSpaceCast:
169 if (!canVectorizeInst(cast<Instruction>(AllocaUser)))
187 if (!canVectorizeInst(cast<Instruction>(GEPUser))
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| SIShrinkInstructions.cpp | 30 "Number of 64-bit instruction reduced to 32-bit.");
91 // Can't shrink instruction with three operands.
123 /// instruction and then folds the literal constant into the instruction if it
124 /// can. This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
139 // Only one literal constant is allowed per instruction, so if src0 is a
146 // SGPR, we cannot commute the instruction, so we can't fold any literal
172 // We have failed to fold src0, so commute the instruction and try again.
210 // Try commuting the instruction and see if that enables us to shrink
217 // getVOPe32 could be -1 here if we started with an instruction that ha
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| /external/llvm/utils/TableGen/ |
| CodeGenInstruction.h | 1 //===- CodeGenInstruction.h - Instruction Class Wrapper ---------*- C++ -*-===//
10 // This file defines a wrapper class for the 'Instruction' TableGen class.
63 /// operand list for a tablegen instruction.
131 /// elements in the instruction's (outs) list.
160 /// non-empty name. If the instruction does not have an operand with the
164 /// hasOperandNamed - Query whether the instruction has an operand of the
208 Record *TheDef; // The actual record defining this instruction.
209 std::string Namespace; // The namespace the instruction is in.
212 /// instruction.
216 /// to the instruction
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| /frameworks/compile/slang/BitWriter_2_9_func/ |
| BitcodeWriter.cpp | 65 default: llvm_unreachable("Unknown cast instruction!");
66 case Instruction::Trunc : return bitc::CAST_TRUNC;
67 case Instruction::ZExt : return bitc::CAST_ZEXT;
68 case Instruction::SExt : return bitc::CAST_SEXT;
69 case Instruction::FPToUI : return bitc::CAST_FPTOUI;
70 case Instruction::FPToSI : return bitc::CAST_FPTOSI;
71 case Instruction::UIToFP : return bitc::CAST_UITOFP;
72 case Instruction::SIToFP : return bitc::CAST_SITOFP;
73 case Instruction::FPTrunc : return bitc::CAST_FPTRUNC;
74 case Instruction::FPExt : return bitc::CAST_FPEXT
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| /frameworks/compile/slang/BitWriter_3_2/ |
| BitcodeWriter.cpp | 65 default: llvm_unreachable("Unknown cast instruction!");
66 case Instruction::Trunc : return bitc::CAST_TRUNC;
67 case Instruction::ZExt : return bitc::CAST_ZEXT;
68 case Instruction::SExt : return bitc::CAST_SEXT;
69 case Instruction::FPToUI : return bitc::CAST_FPTOUI;
70 case Instruction::FPToSI : return bitc::CAST_FPTOSI;
71 case Instruction::UIToFP : return bitc::CAST_UITOFP;
72 case Instruction::SIToFP : return bitc::CAST_SITOFP;
73 case Instruction::FPTrunc : return bitc::CAST_FPTRUNC;
74 case Instruction::FPExt : return bitc::CAST_FPEXT
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| /external/llvm/lib/Analysis/ |
| ValueTracking.cpp | 91 // context (the context instruction provides that context). If an assume and
92 // the context instruction are not in the same block then the DT helps in
97 const Instruction *CxtI;
100 Query(AssumptionCache *AC = nullptr, const Instruction *CxtI = nullptr,
111 // Given the provided Value and, potentially, a context instruction, return
112 // the preferred context instruction (if any).
113 static const Instruction *safeCxtI(const Value *V, const Instruction *CxtI) {
114 // If we've been provided with a context instruction, then use that (provided
119 // If the value is really an already-inserted instruction, then use that
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| InstructionSimplify.cpp | 1 //===- InstructionSimplify.cpp - Fold instruction operands ----------------===//
52 const Instruction *CxtI;
56 const Instruction *cxti = nullptr)
104 Instruction *I = dyn_cast<Instruction>(V);
124 // Otherwise, if the instruction is in the entry block, and is not an invoke,
141 Instruction::BinaryOps OpcodeToExpand = (Instruction::BinaryOps)OpcToExpand;
156 if ((L == A && R == B) || (Instruction::isCommutative(OpcodeToExpand)
179 if ((L == B && R == C) || (Instruction::isCommutative(OpcodeToExpand
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| /external/llvm/lib/CodeGen/ |
| TwoAddressInstructionPass.cpp | 1 //===-- TwoAddressInstructionPass.cpp - Two-Address instruction pass ------===//
10 // This file implements the TwoAddress instruction pass which is used
26 // address instruction is removed.
170 "Two-Address instruction pass", false, false)
173 "Two-Address instruction pass", false, false)
179 /// sink3AddrInstruction - A two-address instruction has been converted to a
180 /// three-address instruction to avoid clobbering a register. Try to sink it
181 /// past the instruction that would kill the above mentioned register to reduce
187 // instruction? After this transformation is done, we no longer need
188 // the instruction to be in three-address form
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| LexicalScopes.cpp | 52 /// extractLexicalScopes - Extract instruction ranges for each lexical scopes
58 // Scan each instruction and create scopes. First build working set of scopes.
64 // Check if instruction has valid location information.
71 // If scope has not changed then skip this instruction.
77 // Ignore DBG_VALUE. It does not contribute to any instruction in output.
82 // If we have already seen a beginning of an instruction range and
83 // current instruction scope does not match scope of first instruction
84 // in this range then create a new instruction range.
90 // This is a beginning of a new instruction range
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| /art/compiler/dex/quick/arm/ |
| codegen_arm.h | 62 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
143 void GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
145 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
151 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
153 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
155 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
157 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
159 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src);
233 bool InexpensiveConstantInt(int32_t value, Instruction::Code opcode) OVERRIDE;
253 * @returns Call instruction
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| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 10 // This file describes the structures used for instruction
12 // schedulers to determine instruction stages and latencies.
26 /// the execution of an instruction. Cycles represents the number of
48 /// indicate that the instruction requires multiple stages at the
52 /// - FUs which instruction actually requires
53 /// - FUs which instruction just reserves. Reserved unit is not available for
54 /// execution of other instruction. However, several instructions can reserve
56 /// Such two types of units reservation is used to model instruction domain
93 /// An itinerary represents the scheduling information for an instruction.
94 /// This includes a set of stages occupied by the instruction and the pipelin
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| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | 626 case Instruction::GetElementPtr: {
636 case Instruction::Trunc: {
642 case Instruction::ZExt: {
648 case Instruction::SExt: {
654 case Instruction::FPTrunc: {
660 case Instruction::FPExt:{
666 case Instruction::UIToFP: {
681 case Instruction::SIToFP: {
696 case Instruction::FPToUI: // double->APInt conversion handles sign
697 case Instruction::FPToSI:
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILPeepholeOptimizer.cpp | 53 // Function to initiate all of the instruction level optimizations.
73 // Run a series of tests to see if we can optimize a CALL instruction.
76 bool optimizeBitExtract(Instruction *inst);
78 bool optimizeBitInsert(Instruction *inst);
79 bool setupBitInsert(Instruction *base,
80 Instruction *&src,
83 // Expand the bit field insert instruction on versions of OpenCL that
86 // Expand the bit field mask instruction on version of OpenCL that
105 bool correctMisalignedMemOp(Instruction *inst);
300 Instruction *inst = (*bbb)
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| /external/v8/src/compiler/ |
| instruction-selector.h | 11 #include "src/compiler/instruction.h"
39 Instruction* Emit(InstructionCode opcode, InstructionOperand* output,
41 Instruction* Emit(InstructionCode opcode, InstructionOperand* output,
44 Instruction* Emit(InstructionCode opcode, InstructionOperand* output,
47 Instruction* Emit(InstructionCode opcode, InstructionOperand* output,
51 Instruction* Emit(InstructionCode opcode, InstructionOperand* output,
55 Instruction* Emit(InstructionCode opcode, size_t output_count,
59 Instruction* Emit(Instruction* instr);
100 // instruction. A node can be covered if the {user} of the node has the onl
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| /external/v8/src/mips64/ |
| simulator-mips64.cc | 74 void Stop(Instruction* instr);
94 bool SetBreakpoint(Instruction* breakpc);
95 bool DeleteBreakpoint(Instruction* breakpc);
120 void MipsDebugger::Stop(Instruction* instr) {
139 // Overwrite the instruction and address with nops.
144 sim_->set_pc(sim_->get_pc() + 3 * Instruction::kInstructionSize);
150 #define UNSUPPORTED() printf("Unsupported instruction.\n");
155 void MipsDebugger::Stop(Instruction* instr) {
160 Instruction::kInstrSize);
167 sim_->set_pc(sim_->get_pc() + 3 * Instruction::kInstrSize)
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| /art/tools/dexfuzz/src/dexfuzz/program/ |
| CodeTranslator.java | 23 import dexfuzz.rawdex.Instruction;
72 // Temporary map from bytecode offset -> instruction.
75 List<Instruction> inputInsns = codeItem.insns;
79 for (Instruction insn : inputInsns) {
100 // Calculate the offsets for each instruction.
168 List<Instruction> outputInsns = new LinkedList<Instruction>();
192 for (Instruction insn : outputInsns) {
302 "Couldn't find a mutatable instruction at handler offset 0x%x",
338 // Find the first instruction that comes after that does not overla
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| /external/llvm/lib/Target/AArch64/ |
| AArch64PromoteConstant.cpp | 15 // constant pool during instruction selection already; therefore, the access
120 typedef DenseMap<Instruction *, Uses> InsertionPoints;
126 Instruction *findInsertionPoint(Use &Use);
135 /// \pre NewPt and all instruction in InsertPts belong to the same function
138 bool isDominated(Instruction *NewPt, Use &Use, InsertionPoints &InsertPts);
147 /// \pre NewPt and all instruction in InsertPts belong to the same function
152 bool tryAndMerge(Instruction *NewPt, Use &Use, InsertionPoints &InsertPts);
186 static void appendAndTransferDominatedUses(Instruction *NewPt, Use &Use,
195 Instruction *OldInstr = IPI->first;
234 /// Check if the given use (Instruction + OpIdx) of Cst should be converted int
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| /external/llvm/lib/Transforms/Scalar/ |
| LoopRotation.cpp | 57 // LCSSA form makes instruction renaming easier.
136 /// these instruction that were outside of the loop, we have to insert PHI nodes
165 // Visit each use of the OrigHeader instruction.
176 Instruction *UserInst = cast<Instruction>(U.getUser());
201 /// heuristics. We handle a single arithmetic instruction along with any type
222 case Instruction::GetElementPtr:
227 case Instruction::Add:
228 case Instruction::Sub:
229 case Instruction::And
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| /external/llvm/tools/llvm-stress/ |
| llvm-stress.cpp | 18 #include "llvm/IR/Instruction.h"
135 /// Add a new instruction.
336 Instruction* Term = BB->getTerminator();
338 Instruction::BinaryOps Op;
342 case 0:{Op = (isFloat?Instruction::FAdd : Instruction::Add); break; }
343 case 1:{Op = (isFloat?Instruction::FSub : Instruction::Sub); break; }
344 case 2:{Op = (isFloat?Instruction::FMul : Instruction::Mul); break;
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| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 118 Instruction::BinaryOps Opcode = I.getOpcode();
119 if (Opcode != Instruction::Add &&
120 Opcode != Instruction::Sub) {
135 if (Opcode == Instruction::Add) {
181 Instruction::BinaryOps Opcode = I.getOpcode();
327 static bool LeftDistributesOverRight(Instruction::BinaryOps LOp,
328 Instruction::BinaryOps ROp) {
333 case Instruction::And:
338 case Instruction::Or:
339 case Instruction::Xor
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