| /libcore/dom/src/test/java/org/w3c/domts/level1/core/ |
| nodeprocessinginstructionnodevalue.java | 32 * Processing Instruction Node is the content of the
33 * Processing Instruction(exclude the target).
35 * Retrieve the Processing Instruction node in the XML file
|
| /ndk/tests/build/issue17144-byteswap/ |
| build.sh | 27 fail_panic "armeabi-v7a doesn't use rev16 instruction for __swap16()"
37 fail_panic "x86 doesn't use rorw instruction for __swap16()"
49 fail_panic "mips doesn't use wsbh instruction for __swap16()"
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/sysroot/usr/include/asm/ |
| vm86.h | 34 - IO-instruction or similar */
35 #define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
36 #define VM86_STI 3 /* sti/popf/iret instruction enabled
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/i386-linux-gnu/asm/ |
| vm86.h | 34 - IO-instruction or similar */
35 #define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
36 #define VM86_STI 3 /* sti/popf/iret instruction enabled
|
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/sysroot/usr/include/x86_64-linux-gnu/asm/ |
| vm86.h | 34 - IO-instruction or similar */
35 #define VM86_INTx 2 /* int3/int x instruction (ARG = x) */
36 #define VM86_STI 3 /* sti/popf/iret instruction enabled
|
| /system/extras/perfprofd/ |
| perf_profile.proto | 11 // Address here is the offset of the instruction address to the load address
32 // Start instruction address of a range.
35 // If "end" and "to" is not provided, "start" represents a single instruction.
|
| /external/llvm/include/llvm/Analysis/ |
| AliasAnalysis.h | 140 /// the given instruction.
148 Location getLocation(const Instruction *Inst) {
159 llvm_unreachable("unsupported memory instruction");
369 /// instruction may read or write memory (without regard to a
371 ModRefResult getModRefInfo(const Instruction *I) {
386 /// getModRefInfo - Return information about whether or not an instruction may
387 /// read or write the specified memory location. An instruction
389 ModRefResult getModRefInfo(const Instruction *I,
392 case Instruction::VAArg: return getModRefInfo((const VAArgInst*)I, Loc);
393 case Instruction::Load: return getModRefInfo((const LoadInst*)I, Loc)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| EarlyCSE.cpp | 53 Instruction *Inst;
55 SimpleValue(Instruction *I) : Inst(I) {
60 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() ||
61 Inst == DenseMapInfo<Instruction *>::getTombstoneKey();
64 static bool canHandle(Instruction *Inst) {
80 return DenseMapInfo<Instruction *>::getEmptyKey();
83 return DenseMapInfo<Instruction *>::getTombstoneKey();
91 Instruction *Inst = Val.Inst;
138 "Invalid/unknown instruction");
147 Instruction *LHSI = LHS.Inst, *RHSI = RHS.Inst
[all...] |
| Scalarizer.cpp | 40 typedef SmallVector<std::pair<Instruction *, ValueVector *>, 16> GatherList;
138 // InstVisitor methods. They return true if the instruction was scalarized,
140 bool visitInstruction(Instruction &) { return false; }
164 Scatterer scatter(Instruction *, Value *);
165 void gather(Instruction *, const ValueVector &);
167 void transferMetadata(Instruction *, const ValueVector &);
171 template<typename T> bool splitBinary(Instruction &, const T &);
253 Instruction *I = II;
265 Scatterer Scalarizer::scatter(Instruction *Point, Value *V) {
273 if (Instruction *VOp = dyn_cast<Instruction>(V))
[all...] |
| /art/runtime/verifier/ |
| register_line.h | 27 class Instruction;
50 // During verification, we associate one of these with every "interesting" instruction. We track
192 const RegType& GetInvocationThis(MethodVerifier* verifier, const Instruction* inst,
197 * Verify types for a simple two-register instruction (e.g. "neg-int").
200 void CheckUnaryOp(MethodVerifier* verifier, const Instruction* inst, const RegType& dst_type,
204 void CheckUnaryOpWide(MethodVerifier* verifier, const Instruction* inst,
209 void CheckUnaryOpToWide(MethodVerifier* verifier, const Instruction* inst,
214 void CheckUnaryOpFromWide(MethodVerifier* verifier, const Instruction* inst,
220 * Verify types for a simple three-register instruction (e.g. "add-int").
224 void CheckBinaryOp(MethodVerifier* verifier, const Instruction* inst
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86DisassemblerDecoder.h | 11 // It contains the public interface of the instruction decoder.
25 // Accessor functions for various fields of an Intel instruction
493 /// the decoder. Reads a single byte from the instruction's address space.
498 /// \param address The address in the instruction's address space that should
511 /// The specification for how to extract and interpret a full instruction and
517 /// The x86 internal instruction, which is produced by the decoder.
531 // General instruction information
535 // The start of the instruction, usable with the reader
537 // The length of the instruction, in bytes
566 // Offsets from the start of the instruction to the pieces of data, which i
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_bb.cpp | 61 delete_Instruction(prog, reinterpret_cast<Instruction *>(it.get()));
97 for (Instruction *i = getFirst(); i; i = i->next)
118 BasicBlock::insertHead(Instruction *inst)
152 BasicBlock::insertTail(Instruction *inst)
182 BasicBlock::insertBefore(Instruction *q, Instruction *p)
212 BasicBlock::insertAfter(Instruction *p, Instruction *q)
235 BasicBlock::remove(Instruction *insn)
266 void BasicBlock::permuteAdjacent(Instruction *a, Instruction *b
[all...] |
| /external/mockito/cglib-and-asm/src/org/mockito/asm/tree/analysis/ |
| Analyzer.java | 92 * instruction of the method. The size of the returned array is
95 * instruction cannot be reached (dead code).
114 // computes exception handlers for each instruction
129 // computes the subroutine for each instruction:
232 throw new AnalyzerException("RET instruction outside of a sub routine");
289 throw new AnalyzerException("Error at instruction " + insn
292 throw new AnalyzerException("Error at instruction " + insn
347 // if insn does not falls through to the next instruction, return.
367 * Returns the symbolic stack frame for each instruction of the last
371 * instruction of the method. The size of the returned array is
[all...] |
| /external/valgrind/none/tests/mips64/ |
| branch_and_jump_instructions.c | 107 #define TEST3(instruction, RDval, RSval, RTval, RD, RS, RT) \
115 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
118 "end"instruction#RDval":" "\n\t" \
126 printf(instruction" :: out: 0x%llx, RSval: 0x%llx, RTval: 0x%llx\n", \
130 #define TEST4(instruction, RDval, RSval, RD, RS) \
137 instruction" $"#RS", end"instruction#RDval "\n\t" \
140 "end"instruction#RDval":" "\n\t" \
148 printf(instruction" :: out: 0x%llx, RSval: 0x%llx\n",
[all...] |
| branches.c | 130 #define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \
138 instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
141 "end"instruction#RDval":" "\n\t" \
149 printf(instruction" :: out: %d, RDval: %d, RSval: %d, RTval: %d\n", \
153 #define TESTINST5(instruction, RDval, RSval, RD, RS) \
160 instruction" $"#RS", end"instruction#RDval "\n\t" \
163 "end"instruction#RDval":" "\n\t" \
171 printf(instruction" :: out: %d, RDval: %d, RSval: %d\n",
[all...] |
| /art/compiler/dex/quick/x86/ |
| int_x86.cc | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 25 /// specified instruction is a constant integer. If so, check to see if there
28 static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
30 assert(I && "No instruction?");
42 // This instruction is producing bits that are not demanded. Shrink the RHS.
48 // Remove 'nsw' and 'nuw' from the instruction in this case.
50 assert(OBO->getOpcode() == Instruction::Add);
64 /// SimplifyDemandedInstructionBits - Inst is an integer instruction that
65 /// SimplifyDemandedBits knows about. See if the instruction has any
67 bool InstCombiner::SimplifyDemandedInstructionBits(Instruction &Inst) {
81 /// specified instruction operand if possible, updating it in place. It return
[all...] |
| /external/vixl/src/vixl/a64/ |
| disasm-a64.cc | 62 void Disassembler::VisitAddSubImmediate(const Instruction* instr) {
107 void Disassembler::VisitAddSubShifted(const Instruction* instr) {
154 void Disassembler::VisitAddSubExtended(const Instruction* instr) {
192 void Disassembler::VisitAddSubWithCarry(const Instruction* instr) {
227 void Disassembler::VisitLogicalImmediate(const Instruction* instr) {
234 // The immediate encoded in the instruction is not in the expected format.
299 void Disassembler::VisitLogicalShifted(const Instruction* instr) {
350 void Disassembler::VisitConditionalCompareRegister(const Instruction* instr) {
365 void Disassembler::VisitConditionalCompareImmediate(const Instruction* instr) {
380 void Disassembler::VisitConditionalSelect(const Instruction* instr)
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-thumbv7.txt | 21 # CHECK: warning: invalid instruction encoding
29 # CHECK: potentially undefined instruction encoding
32 [0x50 0xbf] # hint #5; legal as the third instruction for the iteee above
36 # CHECK: potentially undefined instruction encoding
38 # CHECK: potentially undefined instruction encoding
47 # CHECK: potentially undefined instruction encoding
83 # CHECK: potentially undefined instruction encoding
93 # CHECK: invalid instruction encoding
98 # CHECK: invalid instruction encoding
103 # CHECK: invalid instruction encodin
[all...] |
| /external/llvm/lib/Analysis/ |
| MemoryDependenceAnalysis.cpp | 107 static void RemoveFromReverseMap(DenseMap<Instruction*,
109 Instruction *Inst, KeyTy Val) {
110 typename DenseMap<Instruction*, SmallPtrSet<KeyTy, 4> >::iterator
119 /// GetLocation - If the given instruction references a specific memory
122 /// instruction.
124 AliasAnalysis::ModRefResult GetLocation(const Instruction *Inst,
214 Instruction *Inst = --ScanIt;
220 // A simple instruction.
246 // If we could not obtain a pointer for the instruction and the instruction
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineLICM.cpp | 15 // constructs that are not exposed before lowering and instruction selection.
169 /// HoistPostRA - When an instruction is found to only use loop invariant
170 /// operands that is safe to hoist, this instruction is called to do the
174 /// ProcessMI - Examine the instruction for potentai LICM candidate. Also
186 /// IsLICMCandidate - Returns true if the instruction may be a suitable
187 /// candidate for LICM. e.g. If the instruction is a call, then it's
191 /// IsLoopInvariantInst - Returns true if the instruction is loop
194 /// and the instruction is hoistable.
198 /// HasLoopPHIUse - Return true if the specified instruction is used by any
211 /// check if hoisting an instruction of the given cost matrix can cause hig
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 115 bool selectAddSub(const Instruction *I);
116 bool selectLogicalOp(const Instruction *I);
117 bool selectLoad(const Instruction *I);
118 bool selectStore(const Instruction *I);
119 bool selectBranch(const Instruction *I);
120 bool selectIndirectBr(const Instruction *I);
121 bool selectCmp(const Instruction *I);
122 bool selectSelect(const Instruction *I);
123 bool selectFPExt(const Instruction *I);
124 bool selectFPTrunc(const Instruction *I)
[all...] |
| AArch64ExpandPseudoInsts.cpp | 36 return "AArch64 pseudo instruction expansion pass";
48 /// \brief Transfer implicit operands on the pseudo instruction to the
87 /// ORR + MOVK instruction sequence.
97 // Create the ORR-immediate instruction.
104 // Create the MOVK instruction.
124 /// can be materialized with an ORR instruction.
132 /// materialize them with a single ORR instruction. The remaining one or two
137 /// an ORR instruction.
159 // materialized with an ORR instruction.
164 // Create the ORR-immediate instruction
[all...] |
| /art/compiler/dex/quick/ |
| dex_file_method_inliner.cc | 126 DCHECK_EQ(Instruction::FormatOf(invoke->dalvikInsn.opcode), Instruction::k35c);
[all...] |
| /art/compiler/dex/quick/arm64/ |
| codegen_arm64.h | 54 bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src,
56 bool HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div,
58 bool HandleEasyDivRem64(Instruction::Code dalvik_opcode, bool is_div,
131 void GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
133 void GenArithImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
139 void GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
141 void GenArithOpDouble(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
143 void GenArithOpFloat(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
145 void GenCmpFP(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src1,
147 void GenConversion(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src) OVERRIDE
[all...] |
