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  /art/compiler/dex/quick/mips/
codegen_mips.h 233 return cu_->target64; // Wide GPRs are formed by pairing on mips32.
236 return cu_->target64; // Wide FPRs are formed by pairing on mips32.
  /development/ndk/platforms/android-21/arch-mips/lib/
libc.a     [all...]
  /ndk/build/tools/
gen-platforms.sh 732 copy_src_directory $PLATFORM_SRC/arch-$ARCH/lib $SYSROOT_DST/lib "mips -mabi=32 -mips32 sysroot libs"
739 copy_src_directory $PLATFORM_SRC/arch-$ARCH/lib $SYSROOT_DST/lib "mips -mabi=32 -mips32 sysroot libs"
765 gen_crt_objects $PLATFORM $ARCH platforms/common/src $PLATFORM_SRC_ARCH $SYSROOT_DST/lib "-mabi=32 -mips32"
772 gen_crt_objects $PLATFORM $ARCH platforms/common/src $PLATFORM_SRC_ARCH $SYSROOT_DST/lib "-mabi=32 -mips32"
794 gen_shared_libraries $ARCH $PLATFORM_SRC/arch-$ARCH/symbols $SYSROOT_DST/lib "-mabi=32 -mips32"
801 gen_shared_libraries $ARCH $PLATFORM_SRC/arch-$ARCH/symbols $SYSROOT_DST/lib "-mabi=32 -mips32"
819 copy_src_directory $PLATFORM_SRC/arch-$ARCH/lib-bootstrap/lib $SYSROOT_DST/lib "mips -mabi=32 -mips32 sysroot libs (boostrap)"
826 copy_src_directory $PLATFORM_SRC/arch-$ARCH/lib-bootstrap/lib $SYSROOT_DST/lib "mips -mabi=32 -mips32 sysroot libs (boostrap)"
    [all...]
  /prebuilts/ndk/9/platforms/android-21/arch-mips/usr/lib/
libc.a     [all...]
  /art/runtime/arch/mips/
instruction_set_features_mips.cc 96 LOG(WARNING) << "Unexpected CPU variant for Mips32 using defaults: " << variant;
  /bionic/libc/arch-mips/include/machine/
elf_machdep.h 143 #define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
  /development/ndk/platforms/android-21/arch-mips/include/machine/
elf_machdep.h 142 #define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
  /development/ndk/platforms/android-21/arch-mips64/include/machine/
elf_machdep.h 142 #define EF_MIPS_ARCH_32 0x50000000 /* -mips32 code */
  /development/ndk/platforms/android-9/arch-mips/include/machine/
asm.h 48 #define _MIPS_ISA_MIPS32 32 /* MIPS32 */
  /external/kernel-headers/original/uapi/asm-mips/asm/
inst.h 623 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
625 struct fb_format { /* FPU branch format (MIPS32) */
634 struct fp0_format { /* FPU multiply and add format (MIPS32) */
655 struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
  /external/libvpx/libvpx/
README 67 mips32-linux-gcc
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCTargetDesc.cpp 51 CPU = "mips32";
  /external/llvm/lib/Target/Mips/
MSA.txt 52 On MIPS32, the copy_u.d intrinsic will emit this instruction instead of
MipsSEISelDAGToDAG.h 10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
  /external/llvm/test/CodeGen/Mips/
eh-return32.ll 1 ; RUN: llc -march=mipsel -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=CHECK -check-prefix=NOT-R6
fpneeded.ll 1 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-os16 | FileCheck %s -check-prefix=32
mips16_32_8.ll 1 ; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=static -O3 < %s -mips-mixed-16-32 | FileCheck %s -check-prefix=32
mno-ldc1-sdc1.ll 2 ; RUN: llc -march=mipsel -mcpu=mips32 < %s | \
11 ; RUN: -mcpu=mips32 < %s | \
25 ; RUN: -mcpu=mips32 < %s | \
39 ; RUN: -mcpu=mips32 < %s | \
zeroreg.ll 1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV
  /external/llvm/test/CodeGen/Mips/llvm-ir/
and.ll 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
or.ll 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
udiv.ll 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
xor.ll 3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
  /external/llvm/test/MC/Disassembler/Mips/msa/
test_i5.txt 1 # RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32 -mattr=+msa | FileCheck %s
  /external/llvm/test/MC/Mips/mips32/
invalid-mips32r2.s 3 # RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32 \

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