1 ; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV 2 ; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMOV 3 ; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32R6 4 ; RUN: llc < %s -march=mipsel -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV 5 ; RUN: llc < %s -march=mipsel -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV 6 ; RUN: llc < %s -march=mipsel -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMOV 7 ; RUN: llc < %s -march=mipsel -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64R6 8 9 @g1 = external global i32 10 11 define i32 @sel_icmp_nez_i32_z0(i32 signext %s) nounwind readonly { 12 entry: 13 ; ALL-LABEL: sel_icmp_nez_i32_z0: 14 15 ; 32-CMOV: lw $2, 0(${{[0-9]+}}) 16 ; 32-CMOV: movn $2, $zero, $4 17 18 ; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 19 ; 32R6: seleqz $2, $[[R0]], $4 20 21 ; 64-CMOV: lw $2, 0(${{[0-9]+}}) 22 ; 64-CMOV: movn $2, $zero, $4 23 24 ; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 25 ; 64R6: seleqz $2, $[[R0]], $4 26 27 %tobool = icmp ne i32 %s, 0 28 %0 = load i32, i32* @g1, align 4 29 %cond = select i1 %tobool, i32 0, i32 %0 30 ret i32 %cond 31 } 32 33 define i32 @sel_icmp_nez_i32_z1(i32 signext %s) nounwind readonly { 34 entry: 35 ; ALL-LABEL: sel_icmp_nez_i32_z1: 36 37 ; 32-CMOV: lw $2, 0(${{[0-9]+}}) 38 ; 32-CMOV: movz $2, $zero, $4 39 40 ; 32R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 41 ; 32R6: selnez $2, $[[R0]], $4 42 43 ; 64-CMOV: lw $2, 0(${{[0-9]+}}) 44 ; 64-CMOV: movz $2, $zero, $4 45 46 ; 64R6: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 47 ; 64R6: selnez $2, $[[R0]], $4 48 49 %tobool = icmp ne i32 %s, 0 50 %0 = load i32, i32* @g1, align 4 51 %cond = select i1 %tobool, i32 %0, i32 0 52 ret i32 %cond 53 } 54 55 @g2 = external global i64 56 57 define i64 @sel_icmp_nez_i64_z0(i64 %s) nounwind readonly { 58 entry: 59 ; ALL-LABEL: sel_icmp_nez_i64_z0: 60 61 ; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}}) 62 ; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}}) 63 ; 32-CMOV-DAG: movn $[[R0]], $zero, $4 64 ; 32-CMOV-DAG: movn $[[R1]], $zero, $4 65 66 ; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 67 ; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 68 ; 32R6-DAG: or $[[CC:[0-9]+]], $4, $5 69 ; 32R6-DAG: seleqz $2, $[[R0]], $[[CC]] 70 ; 32R6-DAG: seleqz $3, $[[R1]], $[[CC]] 71 72 ; 64-CMOV: ld $2, 0(${{[0-9]+}}) 73 ; 64-CMOV: movn $2, $zero, $4 74 75 ; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}}) 76 ; 64R6: seleqz $2, $[[R0]], $4 77 78 %tobool = icmp ne i64 %s, 0 79 %0 = load i64, i64* @g2, align 4 80 %cond = select i1 %tobool, i64 0, i64 %0 81 ret i64 %cond 82 } 83 84 define i64 @sel_icmp_nez_i64_z1(i64 %s) nounwind readonly { 85 entry: 86 ; ALL-LABEL: sel_icmp_nez_i64_z1: 87 88 ; 32-CMOV-DAG: lw $[[R0:2]], 0(${{[0-9]+}}) 89 ; 32-CMOV-DAG: lw $[[R1:3]], 4(${{[0-9]+}}) 90 ; 32-CMOV-DAG: movz $[[R0]], $zero, $4 91 ; 32-CMOV-DAG: movz $[[R1]], $zero, $4 92 93 ; 32R6-DAG: lw $[[R0:[0-9]+]], 0(${{[0-9]+}}) 94 ; 32R6-DAG: lw $[[R1:[0-9]+]], 4(${{[0-9]+}}) 95 ; 32R6-DAG: or $[[CC:[0-9]+]], $4, $5 96 ; 32R6-DAG: selnez $2, $[[R0]], $[[CC]] 97 ; 32R6-DAG: selnez $3, $[[R1]], $[[CC]] 98 99 ; 64-CMOV: ld $2, 0(${{[0-9]+}}) 100 ; 64-CMOV: movz $2, $zero, $4 101 102 ; 64R6: ld $[[R0:[0-9]+]], 0(${{[0-9]+}}) 103 ; 64R6: selnez $2, $[[R0]], $4 104 105 %tobool = icmp ne i64 %s, 0 106 %0 = load i64, i64* @g2, align 4 107 %cond = select i1 %tobool, i64 %0, i64 0 108 ret i64 %cond 109 } 110
