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  /external/llvm/test/CodeGen/PowerPC/
2004-11-30-shr-var-crash.ll 4 %shamt = add i8 0, 1 ; <i8> [#uses=1]
5 %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1]
  /external/llvm/test/CodeGen/X86/
shift-bmi2.ll 4 define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
6 %shl = shl i32 %x, %shamt
28 define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
31 %shl = shl i32 %x, %shamt
55 define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
57 %shl = shl i64 %x, %shamt
73 define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
76 %shl = shl i64 %x, %shamt
93 define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
95 %shl = lshr i32 %x, %shamt
    [all...]
shift-and.ll 12 %shamt = and i32 %t, 31
13 %res = shl i32 %val, %shamt
25 %shamt = and i32 %t, 63
26 %res = shl i32 %val, %shamt
40 %shamt = and i16 %t, 31
42 %tmp1 = ashr i16 %tmp, %shamt
51 %shamt = and i64 %t, 63
52 %res = lshr i64 %val, %shamt
60 %shamt = and i64 %t, 191
61 %res = lshr i64 %val, %shamt
    [all...]
vshift-5.ll 12 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
13 %shl = shl <4 x i32> %val, %shamt
26 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
27 %shr = ashr <4 x i32> %val, %shamt
39 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
40 %shl = shl <4 x i32> %val, %shamt
52 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
53 %shr = ashr <4 x i32> %val, %shamt
vshift-4.ll 10 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
11 %shl = shl <2 x i64> %val, %shamt
26 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
27 %shl = shl <2 x i64> %val, %shamt
36 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
37 %shl = shl <4 x i32> %val, %shamt
46 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
47 %shl = shl <4 x i32> %val, %shamt
56 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
57 %shl = shl <4 x i32> %val, %shamt
    [all...]
  /external/llvm/test/ExecutionEngine/MCJIT/
test-shift.ll 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
  /external/llvm/test/ExecutionEngine/OrcMCJIT/
test-shift.ll 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
  /external/llvm/test/ExecutionEngine/
test-interp-vec-shift.ll 4 %shamt = add <2 x i8> <i8 0, i8 0>, <i8 1, i8 2>
5 %shift.upgrd.1 = zext <2 x i8> %shamt to <2 x i32>
8 %shift.upgrd.2 = zext <2 x i8> %shamt to <2 x i32>
13 %shift.upgrd.5 = zext <2 x i8> %shamt to <2 x i32>
16 %shift.upgrd.6 = zext <2 x i8> %shamt to <2 x i32>
20 %shift.upgrd.7 = zext <2 x i8> %shamt to <2 x i64>
23 %shift.upgrd.8 = zext <2 x i8> %shamt to <2 x i64>
26 %shift.upgrd.9 = zext <2 x i8> %shamt to <2 x i64>
29 %shift.upgrd.10 = zext <2 x i8> %shamt to <2 x i64>
  /external/llvm/lib/Target/Mips/
MipsAnalyzeImmediate.cpp 43 unsigned Shamt = countTrailingZeros(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
45 AddInstr(SeqLs, Inst(SLL, Shamt));
MipsISelLowering.cpp 748 unsigned Shamt = CN->getZExtValue();
753 if ((Shamt != SMPos0) || (SMPos0 + SMSize0 > ValTy.getSizeInBits()))
    [all...]
MipsInstrFormats.td 19 // shamt - only used on shift instructions, contains the shift amount.
126 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
136 bits<5> shamt;
145 let Inst{10-6} = shamt;
246 bits<5> shamt;
255 let Inst{10-6} = shamt;
  /art/compiler/utils/mips64/
assembler_mips64.h 97 void Sll(GpuRegister rd, GpuRegister rt, int shamt);
98 void Srl(GpuRegister rd, GpuRegister rt, int shamt);
99 void Sra(GpuRegister rd, GpuRegister rt, int shamt);
103 void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
104 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
105 void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
106 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
107 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
108 void Dsra32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
344 void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct)
    [all...]
assembler_mips64.cc 34 int shamt, int funct) {
42 shamt << kShamtShift |
252 void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rt, int shamt) {
253 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x00);
256 void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rt, int shamt) {
257 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x02);
260 void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rt, int shamt) {
261 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x03);
276 void Mips64Assembler::Dsll(GpuRegister rd, GpuRegister rt, int shamt) {
277 EmitR(0, static_cast<GpuRegister>(0), rt, rd, shamt, 0x38)
    [all...]
  /art/compiler/utils/mips/
assembler_mips.h 77 void Sll(Register rd, Register rs, int shamt);
78 void Srl(Register rd, Register rs, int shamt);
79 void Sra(Register rd, Register rs, int shamt);
271 void EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct);
assembler_mips.cc 42 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) {
50 shamt << kShamtShift |
231 void MipsAssembler::Sll(Register rd, Register rs, int shamt) {
232 EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x00);
235 void MipsAssembler::Srl(Register rd, Register rs, int shamt) {
236 EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x02);
239 void MipsAssembler::Sra(Register rd, Register rs, int shamt) {
240 EmitR(0, rs, static_cast<Register>(0), rd, shamt, 0x03);
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 607 unsigned ShAmt = SA->getZExtValue();
611 if (ShAmt >= BitWidth)
614 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
619 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
622 int Diff = ShAmt-C1;
636 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
646 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
649 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
653 TLO.DAG.getConstant(ShAmt, ShTy))
    [all...]
LegalizeVectorOps.cpp 554 SDValue Lo, Hi, ShAmt;
557 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
558 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
567 ShAmt = DAG.getConstant(SrcEltBits - BitOffset,
569 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
586 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
588 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
589 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
    [all...]
  /system/core/libpixelflinger/codeflinger/
mips_disassem.c 221 reg_name[i.RType.rt], i.RType.shamt);
224 if (i.RType.func == OP_SRLV && (i.RType.shamt & 1) == 1) {
246 i.RType.shamt);
327 i.RType.shamt);
333 i.RType.shamt);
334 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_WSBH)
338 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEB)
342 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEH)
mips_opcode.h 65 unsigned shamt: 5; member in struct:__anon69945::__anon69948
100 unsigned shamt: 5; member in struct:__anon69945::__anon69952
270 * Values for the 'shamt' field when OP_SPECIAL3 && func OP_BSHFL.
  /external/llvm/lib/Transforms/InstCombine/
InstCombineShifts.cpp 380 Constant *ShAmt = ConstantExpr::getZExt(COp1, TrOp->getType());
382 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
708 unsigned ShAmt = Op1C->getZExtValue();
713 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt),
721 ComputeNumSignBits(I.getOperand(0), 0, &I) > ShAmt) {
751 unsigned ShAmt = Op1C->getZExtValue();
761 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
771 MaskedValueIsZero(Op0, APInt::getLowBitsSet(Op1C->getBitWidth(), ShAmt),
795 unsigned ShAmt = Op1C->getZExtValue();
    [all...]
InstCombineCompares.cpp     [all...]
  /external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp 95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
457 unsigned ShAmt) {
464 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
582 unsigned ShAmt = Log2_32(RHSC);
584 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
610 unsigned ShAmt = 0;
620 ShAmt = Sh->getZExtValue();
621 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
624 ShAmt = 0
    [all...]
  /external/llvm/lib/Transforms/Scalar/
ScalarReplAggregates.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86InstrShiftRotate.td     [all...]
  /external/clang/lib/Lex/
PPExpressions.cpp 613 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
614 if (ShAmt >= LHS.getBitWidth())
615 Overflow = true, ShAmt = LHS.getBitWidth()-1;
616 Res = LHS.Val >> ShAmt;

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