| /external/skia/tests/ |
| CPlusPlusEleven.cpp | 25 Moveable src2, dst2; dst2 = Move(src2); local
|
| /external/llvm/lib/Target/X86/ |
| X86InstrSSE.td | 247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"))
[all...] |
| X86InstrAVX512.td | 416 (ins VR512:$src1, From.RC:$src2, u8imm:$src3),
418 "\t{$src3, $src2, $src1, $dst|"
419 "$dst, $src1, $src2, $src3}",
421 (From.VT From.RC:$src2),
427 (ins VR512:$src1, From.MemOp:$src2, u8imm:$src3),
429 "\t{$src3, $src2, $src1, $dst|"
430 "$dst, $src1, $src2, $src3}",
448 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
450 VR512:$src1, From.RC:$src2,
489 (ins VR128X:$src1, VR128X:$src2, u8imm:$src3)
[all...] |
| X86InstrCompiler.td | 554 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
556 "{$src2, $dst|$dst, $src2}"),
560 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
562 "{$src2, $dst|$dst, $src2}"),
566 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
568 "{$src2, $dst|$dst, $src2}"),
572 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
[all...] |
| X86InstrMMX.td | 99 (ins VR64:$src1, VR64:$src2),
100 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
101 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))], itins.rr>,
106 (ins VR64:$src1, i64mem:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
109 (bitconvert (load_mmx addr:$src2))))],
117 (ins VR64:$src1, VR64:$src2),
118 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}")
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| int-cmp-38.ll | 16 %src2 = load i32 , i32 *@g
17 %cond = icmp slt i32 %src1, %src2
34 %src2 = load i32 , i32 *@g
35 %cond = icmp ult i32 %src1, %src2
52 %src2 = load i32 , i32 *@g
53 %cond = icmp eq i32 %src1, %src2
70 %src2 = load i32 , i32 *@g
71 %cond = icmp ne i32 %src1, %src2
89 %src2 = load i32 , i32 *@h, align 2
90 %cond = icmp slt i32 %src1, %src2
[all...] |
| memcmp-02.ll | 5 declare i64 @memcmp(i8 *%src1, i8 *%src2, i64 %size)
8 define i64 @f1(i8 *%src1, i8 *%src2) {
12 %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 0)
17 define i64 @f2(i8 *%src1, i8 *%src2) {
25 %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 2)
30 define void @f3(i8 *%src1, i8 *%src2, i64 *%dest) {
35 %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 3)
48 define void @f4(i8 *%src1, i8 *%src2, i64 *%dest) {
54 %res = call i64 @memcmp(i8 *%src1, i8 *%src2, i64 4)
67 define void @f5(i8 *%src1, i8 *%src2, i64 *%dest)
[all...] |
| strcmp-01.ll | 5 declare signext i32 @strcmp(i8 *%src1, i8 *%src2)
8 define i32 @f1(i8 *%src1, i8 *%src2) {
19 %res = call i32 @strcmp(i8 *%src1, i8 *%src2)
24 define void @f2(i8 *%src1, i8 *%src2, i32 *%dest) {
33 %res = call i32 @strcmp(i8 *%src1, i8 *%src2)
47 define i32 @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
60 %res = call i32 @strcmp(i8 *%src1, i8 *%src2)
|
| strcmp-02.ll | 5 declare i64 @strcmp(i8 *%src1, i8 *%src2)
8 define i64 @f1(i8 *%src1, i8 *%src2) {
20 %res = call i64 @strcmp(i8 *%src1, i8 *%src2)
25 define void @f2(i8 *%src1, i8 *%src2, i64 *%dest) {
34 %res = call i64 @strcmp(i8 *%src1, i8 *%src2)
48 define i64 @f3(i8 *%src1, i8 *%src2, i64 *%dest) {
62 %res = call i64 @strcmp(i8 *%src1, i8 *%src2)
|
| memcmp-01.ll | 5 declare signext i32 @memcmp(i8 *%src1, i8 *%src2, i64 %size)
8 define i32 @f1(i8 *%src1, i8 *%src2) {
12 %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 0)
17 define i32 @f2(i8 *%src1, i8 *%src2) {
24 %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 2)
29 define void @f3(i8 *%src1, i8 *%src2, i32 *%dest) {
34 %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 3)
47 define void @f4(i8 *%src1, i8 *%src2, i32 *%dest) {
53 %res = call i32 @memcmp(i8 *%src1, i8 *%src2, i64 4)
66 define void @f5(i8 *%src1, i8 *%src2, i32 *%dest)
[all...] |
| int-cmp-36.ll | 17 %src2 = sext i16 %val to i32
18 %cond = icmp slt i32 %src1, %src2
35 %src2 = sext i16 %val to i32
36 %cond = icmp ult i32 %src1, %src2
54 %src2 = sext i16 %val to i32
55 %cond = icmp eq i32 %src1, %src2
73 %src2 = sext i16 %val to i32
74 %cond = icmp ne i32 %src1, %src2
93 %src2 = sext i16 %val to i32
94 %cond = icmp slt i32 %src1, %src2
[all...] |
| int-cmp-37.ll | 17 %src2 = zext i16 %val to i32
18 %cond = icmp ult i32 %src1, %src2
35 %src2 = zext i16 %val to i32
36 %cond = icmp slt i32 %src1, %src2
54 %src2 = zext i16 %val to i32
55 %cond = icmp eq i32 %src1, %src2
73 %src2 = zext i16 %val to i32
74 %cond = icmp ne i32 %src1, %src2
93 %src2 = zext i16 %val to i32
94 %cond = icmp ult i32 %src1, %src2
[all...] |
| int-cmp-39.ll | 17 %src2 = sext i16 %val to i64
18 %cond = icmp slt i64 %src1, %src2
35 %src2 = sext i16 %val to i64
36 %cond = icmp ult i64 %src1, %src2
54 %src2 = sext i16 %val to i64
55 %cond = icmp eq i64 %src1, %src2
73 %src2 = sext i16 %val to i64
74 %cond = icmp ne i64 %src1, %src2
93 %src2 = sext i16 %val to i64
94 %cond = icmp slt i64 %src1, %src2
[all...] |
| int-cmp-40.ll | 17 %src2 = zext i16 %val to i64
18 %cond = icmp ult i64 %src1, %src2
35 %src2 = zext i16 %val to i64
36 %cond = icmp slt i64 %src1, %src2
54 %src2 = zext i16 %val to i64
55 %cond = icmp eq i64 %src1, %src2
73 %src2 = zext i16 %val to i64
74 %cond = icmp ne i64 %src1, %src2
93 %src2 = zext i16 %val to i64
94 %cond = icmp ult i64 %src1, %src2
[all...] |
| int-cmp-41.ll | 17 %src2 = sext i32 %val to i64
18 %cond = icmp slt i64 %src1, %src2
35 %src2 = sext i32 %val to i64
36 %cond = icmp ult i64 %src1, %src2
54 %src2 = sext i32 %val to i64
55 %cond = icmp eq i64 %src1, %src2
73 %src2 = sext i32 %val to i64
74 %cond = icmp ne i64 %src1, %src2
93 %src2 = sext i32 %val to i64
94 %cond = icmp slt i64 %src1, %src2
[all...] |
| int-cmp-42.ll | 17 %src2 = zext i32 %val to i64
18 %cond = icmp ult i64 %src1, %src2
35 %src2 = zext i32 %val to i64
36 %cond = icmp slt i64 %src1, %src2
54 %src2 = zext i32 %val to i64
55 %cond = icmp eq i64 %src1, %src2
73 %src2 = zext i32 %val to i64
74 %cond = icmp ne i64 %src1, %src2
93 %src2 = zext i32 %val to i64
94 %cond = icmp ult i64 %src1, %src2
[all...] |
| int-cmp-43.ll | 16 %src2 = load i64 , i64 *@g
17 %cond = icmp slt i64 %src1, %src2
34 %src2 = load i64 , i64 *@g
35 %cond = icmp ult i64 %src1, %src2
52 %src2 = load i64 , i64 *@g
53 %cond = icmp eq i64 %src1, %src2
70 %src2 = load i64 , i64 *@g
71 %cond = icmp ne i64 %src1, %src2
89 %src2 = load i64 , i64 *@h, align 4
90 %cond = icmp slt i64 %src1, %src2
[all...] |
| /external/bison/lib/ |
| bitset_stats.c | 460 bitset_stats_and (bitset dst, bitset src1, bitset src2)
462 BITSET_CHECK3_ (dst, src1, src2);
463 BITSET_AND_ (dst->s.bset, src1->s.bset, src2->s.bset);
468 bitset_stats_and_cmp (bitset dst, bitset src1, bitset src2)
470 BITSET_CHECK3_ (dst, src1, src2);
471 return BITSET_AND_CMP_ (dst->s.bset, src1->s.bset, src2->s.bset);
476 bitset_stats_andn (bitset dst, bitset src1, bitset src2)
478 BITSET_CHECK3_ (dst, src1, src2);
479 BITSET_ANDN_ (dst->s.bset, src1->s.bset, src2->s.bset);
484 bitset_stats_andn_cmp (bitset dst, bitset src1, bitset src2)
[all...] |
| bitset.c | 409 bitset_op4_cmp (bitset dst, bitset src1, bitset src2, bitset src3,
428 bitset_or (tmp, src1, src2);
433 bitset_and (tmp, src1, src2);
438 bitset_andn (tmp, src1, src2);
448 /* DST = (SRC1 & SRC2) | SRC3. */
450 bitset_and_or_ (bitset dst, bitset src1, bitset src2, bitset src3)
452 bitset_and_or_cmp_ (dst, src1, src2, src3);
456 /* DST = (SRC1 & SRC2) | SRC3. Return non-zero if
457 DST != (SRC1 & SRC2) | SRC3. */
459 bitset_and_or_cmp_ (bitset dst, bitset src1, bitset src2, bitset src3
[all...] |
| /art/test/077-method-override/src2/ |
| Base.java | 26 /* src2: removed */
41 /* src2: public */
56 /* src2: public */
71 /* src2: non-static */
|
| /external/llvm/test/CodeGen/X86/ |
| vsplit-and.ll | 3 define void @t0(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly {
8 %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer
15 define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly {
20 %cmp2 = icmp ne <3 x i64> %src2, zeroinitializer
|
| /frameworks/av/media/libeffects/lvm/lib/Common/src/ |
| MixSoft_2St_D32C31_SAT.c | 32 const LVM_INT32 *src2,
46 src2, dst, n);
57 src2, dst, n);
61 Core_MixHard_2St_D32C31_SAT( pInstance, src1, src2, dst, n);
|
| /external/opencv/cv/src/ |
| _cvmatrix.h | 63 #define icvAddMatrix_32f( src1, src2, dst, w, h ) \
64 icvAddVector_32f( (src1), (src2), (dst), (w)*(h))
66 #define icvSubMatrix_32f( src1, src2, dst, w, h ) \
67 icvSubVector_32f( (src1), (src2), (dst), (w)*(h))
91 CV_INLINE double icvDotProduct_32f( const float* src1, const float* src2, int len )
94 for( int i = 0; i < len; i++ ) s += src1[i]*src2[i];
102 CV_INLINE double icvDotProduct_64f( const double* src1, const double* src2, int len )
105 for( int i = 0; i < len; i++ ) s += src1[i]*src2[i];
113 CV_INLINE void icvMulVectors_32f( const float* src1, const float* src2,
118 dst[i] = src1[i] * src2[i]
[all...] |
| /external/libavc/common/arm/ |
| ih264_inter_pred_luma_bilinear_a9q.s | 137 vld1.8 {q2}, [r1], r4 @// Load row0 ;src2
140 vld1.8 {q3}, [r1], r4 @// Load row1 ;src2
146 vld1.8 {q6}, [r1], r4 @// Load row2 ;src2
148 vld1.8 {q7}, [r1], r4 @// Load row3 ;src2
163 vld1.8 {q2}, [r1], r4 @// Load row4 ;src2
165 vld1.8 {q3}, [r1], r4 @// Load row5 ;src2
175 vld1.8 {q6}, [r1], r4 @// Load row6 ;src2
177 vld1.8 {q7}, [r1], r4 @// Load row7 ;src2
189 vld1.8 {q2}, [r1], r4 @// Load row8 ;src2
201 vld1.8 {q3}, [r1], r4 @// Load row9 ;src2
[all...] |
| /art/test/077-method-override/src/ |
| Base.java | 26 /* src2: removed */
41 /* src2: public */
56 /* src2: public */
71 /* src2: non-static */
79 /* src2: static */
|
