| /external/pcre/dist/sljit/ |
| sljitNativeARM_32.c | 511 sljit_uw src2; local
513 src2 = get_imm(new_constant);
514 if (src2) {
515 *inst = 0xe3a00000 | (ldr_literal & 0xf000) | src2;
522 src2 = get_imm(~new_constant);
523 if (src2) {
524 *inst = 0xe3e00000 | (ldr_literal & 0xf000) | src2;
818 #define EMIT_DATA_PROCESS_INS(opcode, set_flags, dst, src1, src2) \
819 (0xe0000000 | ((opcode) << 21) | (set_flags) | RD(dst) | RN(src1) | (src2))
824 sljit_si src2, sljit_sw src2w)
[all...] |
| sljitNativePPC_common.c | [all...] |
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| sad_inline.h | 39 __inline int32 sad_4pixel(int32 src1, int32 src2, int32 mask)
43 x7 = src2 ^ src1; /* check odd/even combination */
44 if ((uint32)src2 >= (uint32)src1)
46 src1 = src2 - src1; /* subs */
50 src1 = src1 - src2;
186 __inline int32 sad_4pixel(int32 src1, int32 src2, int32 mask)
192 EOR x7, src2, src1; /* check odd/even combination */ local
193 SUBS src1, src2, src1; local
205 __inline int32 sad_4pixelN(int32 src1, int32 src2, int32 mask)
211 EOR x7, src2, src1; /* check odd/even combination * local
212 ADDS src1, src2, src1; local
[all...] |
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_inline.h | 42 __inline int32 sad_4pixel(int32 src1, int32 src2, int32 mask)
46 x7 = src2 ^ src1; /* check odd/even combination */
47 if ((uint32)src2 >= (uint32)src1)
49 src1 = src2 - src1; /* subs */
53 src1 = src1 - src2;
189 __inline int32 sad_4pixel(int32 src1, int32 src2, int32 mask)
195 EOR x7, src2, src1; /* check odd/even combination */ local
196 SUBS src1, src2, src1; local
208 __inline int32 sad_4pixelN(int32 src1, int32 src2, int32 mask)
214 EOR x7, src2, src1; /* check odd/even combination * local
215 ADDS src1, src2, src1; local
[all...] |
| /external/opencv/cv/src/ |
| cvaccum.cpp | 83 ( const srctype *src1, int step1, const srctype *src2, int step2, \
85 (src1, step1, src2, step2, dst, dststep, size) ) \
88 step2 /= sizeof(src2[0]); \
91 for( ; size.height--; src1 += step1, src2 += step2, dst += dststep ) \
96 dsttype t0 = dst[x] + cvtmacro(src1[x])*cvtmacro(src2[x]); \
97 dsttype t1 = dst[x+1] + cvtmacro(src1[x+1])*cvtmacro(src2[x+1]);\
100 t0 = dst[x + 2] + cvtmacro(src1[x + 2])*cvtmacro(src2[x + 2]); \
101 t1 = dst[x + 3] + cvtmacro(src1[x + 3])*cvtmacro(src2[x + 3]); \
106 dst[x] += cvtmacro(src1[x])*cvtmacro(src2[x]); \
190 ( const srctype *src1, int step1, const srctype* src2, int step2,
[all...] |
| cvsamplers.cpp | 224 const srctype *src2 = src + src_step; \
227 src2 -= src_step; \
232 cast_macro(src2[r.x])*b2; \
241 cast_macro(src2[j])*a21 + \
242 cast_macro(src2[j+1])*a22; \
250 cast_macro(src2[r.width])*b2; \
256 src = src2; \
326 const srctype *src2 = src + src_step; \
329 src2 -= src_step; \
334 worktype s1 = cast_macro(src2[r.x*3]);
456 const uchar *src2 = src + src_step; local
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 853 void and_(Register dst, Register src1, const Operand& src2,
856 void eor(Register dst, Register src1, const Operand& src2,
859 void sub(Register dst, Register src1, const Operand& src2,
861 void sub(Register dst, Register src1, Register src2,
863 sub(dst, src1, Operand(src2), s, cond);
866 void rsb(Register dst, Register src1, const Operand& src2,
869 void add(Register dst, Register src1, const Operand& src2,
871 void add(Register dst, Register src1, Register src2,
873 add(dst, src1, Operand(src2), s, cond);
876 void adc(Register dst, Register src1, const Operand& src2,
[all...] |
| macro-assembler-arm.h | 128 void Mls(Register dst, Register src1, Register src2, Register srcA,
130 void And(Register dst, Register src1, const Operand& src2,
320 void Push(Register src1, Register src2, Condition cond = al) {
321 DCHECK(!src1.is(src2));
322 if (src1.code() > src2.code()) {
323 stm(db_w, sp, src1.bit() | src2.bit(), cond);
326 str(src2, MemOperand(sp, 4, NegPreIndex), cond);
331 void Push(Register src1, Register src2, Register src3, Condition cond = al) {
332 DCHECK(!src1.is(src2));
333 DCHECK(!src2.is(src3))
[all...] |
| assembler-arm.cc | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonIntrinsicsV4.td | 70 def : Pat <(int_hexagon_M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2),
71 (M2_vraddh DoubleRegs:$src1, DoubleRegs:$src2)>;
83 Pat <(IntID (i64 DoubleRegs:$src1), immPred:$src2),
84 (MI (i64 DoubleRegs:$src1), immPred:$src2)>;
119 def : Pat <(int_hexagon_M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2,
121 (M4_mpyrr_addr IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
180 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
182 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
186 def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
188 (S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
[all...] |
| /external/vboot_reference/tests/ |
| stateful_util_tests.c | 151 char* src2 = "Howserrr"; local
167 TEST_PTR_EQ(src2, StatefulMemcpy_r(&s, src2, 8),
224 char* src2 = "ThisIsOnlyATest"; local
246 StatefulInit(&s, src2, 16);
249 TEST_PTR_EQ(src2 + 16, s.remaining_buf, "StatefulMemcpy(all) buf");
251 TEST_EQ(0, strcmp(src2, buf), "StatefulMemcpy(all) contents");
257 TEST_PTR_EQ(src2 + 16, s.remaining_buf, "StatefulMemcpy(0) buf");
259 TEST_EQ(0, strcmp(src2, buf), "StatefulMemcpy(0) contents");
266 TEST_EQ(0, strcmp(src2, buf), "StatefulMemcpy(+1) contents")
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZOperators.td | 342 def inserti8 : PatFrag<(ops node:$src1, node:$src2),
343 (or (and node:$src1, -256), node:$src2)>;
344 def insertll : PatFrag<(ops node:$src1, node:$src2),
345 (or (and node:$src1, 0xffffffffffff0000), node:$src2)>;
346 def insertlh : PatFrag<(ops node:$src1, node:$src2),
347 (or (and node:$src1, 0xffffffff0000ffff), node:$src2)>;
348 def inserthl : PatFrag<(ops node:$src1, node:$src2),
349 (or (and node:$src1, 0xffff0000ffffffff), node:$src2)>;
350 def inserthh : PatFrag<(ops node:$src1, node:$src2),
351 (or (and node:$src1, 0x0000ffffffffffff), node:$src2)>;
[all...] |
| SystemZSelectionDAGInfo.h | 42 SDValue Src1, SDValue Src2, SDValue Size,
60 SDValue Src1, SDValue Src2,
|
| /external/v8/src/x64/ |
| macro-assembler-x64.cc | [all...] |
| /bionic/libc/arch-arm64/generic/bionic/ |
| strncmp.S | 41 #define src2 x1 define
69 eor tmp1, src1, src2
85 ldr data2, [src2], #8
177 bic src2, src2, #7
180 ldr data2, [src2], #8
210 ldrb data2w, [src2], #1
|
| /external/icu/icu4c/source/i18n/ |
| ucol.cpp | 115 const uint8_t *src2, int32_t src2Length,
119 src2==NULL || src2Length<-1 || src2Length==0 || (src2Length>0 && src2[src2Length-1]!=0) ||
134 src2Length=(int32_t)uprv_strlen((const char *)src2)+1;
156 /* copy level from src2 not including 00 or 01 */
157 while((b=*src2)>=2) {
158 ++src2;
163 if(*src1==1 && *src2==1) {
165 ++src2;
178 /* src1 is not finished, therefore *src2==0, and src1 is appended *
[all...] |
| /external/llvm/test/TableGen/ |
| TargetInstrInfo.td | 101 def AND8rr : Inst<(ops R8:$dst, R8:$src1, R8:$src2),
102 "and $dst, $src2", 0x20, MRMDestReg,
103 [(set R8:$dst, (and R8:$src1, R8:$src2))]>;
116 "xor $dst, $src2", 0x81, MRM6m,
127 "xor $dst, $src2", 0x81, MRM6m,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrFPStack.td | 130 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src1, RFP32:$src2), TwoArgFP,
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
132 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src1, RFP64:$src2), TwoArgFP,
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
134 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src1, RFP80:$src2), TwoArgFP,
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
143 (ins RFP32:$src1, f32mem:$src2), OneArgFPRW,
145 (OpNode RFP32:$src1, (loadf32 addr:$src2)))]>;
147 (ins RFP64:$src1, f64mem:$src2), OneArgFPRW,
149 (OpNode RFP64:$src1, (loadf64 addr:$src2)))]>;
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_vertprog.c | 381 #define ZERO_SRC_2 (((o_inst->src2 & ~(0xfff << R200_VPI_IN_X_SHIFT)) \
391 #define UNUSED_SRC_2 ((o_inst->src2 & ~15) | 9)
661 o_inst->src2 = UNUSED_SRC_1;
683 o_inst->src2 = UNUSED_SRC_1;
721 o_inst->src2 = UNUSED_SRC_0;
737 o_inst->src2 = UNUSED_SRC_1;
750 o_inst->src2 = UNUSED_SRC_0;
761 o_inst->src2 = UNUSED_SRC_1;
786 o_inst->src2 = MAKE_VSF_SOURCE(t_src_index(vp, &src[1]),
793 o_inst->src2 = t_src(vp, &src[2])
[all...] |
| /external/llvm/test/Bitcode/ |
| conversionInstructions.3.2.ll | 95 define void @bitcast(i32 %src1, i32* %src2){
100 ; CHECK: %res2 = bitcast i32* %src2 to i64*
101 %res2 = bitcast i32* %src2 to i64*
|
| /external/vboot_reference/firmware/lib/include/ |
| utility.h | 50 * Compare [n] bytes in [src1] and [src2].
54 * greater than the first n bytes of [src2]. */
55 int Memcmp(const void *src1, const void *src2, size_t n);
|
| /art/compiler/dex/quick/ |
| mir_to_lir-inl.h | 111 inline LIR* Mir2Lir::NewLIR3(int opcode, int dest, int src1, int src2) {
116 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2);
121 inline LIR* Mir2Lir::NewLIR4(int opcode, int dest, int src1, int src2, int info) {
126 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info);
131 inline LIR* Mir2Lir::NewLIR5(int opcode, int dest, int src1, int src2, int info1,
137 LIR* insn = RawLIR(current_dalvik_offset_, opcode, dest, src1, src2, info1, info2);
|
| /external/bison/lib/ |
| lbitset.c | 1037 lbitset_op3_cmp (bitset dst, bitset src1, bitset src2, enum bitset_ops op)
1040 lbitset_elt *selt2 = LBITSET_HEAD (src2);
1195 lbitset_and_cmp (bitset dst, bitset src1, bitset src2)
1198 lbitset_elt *selt2 = LBITSET_HEAD (src2);
1215 return lbitset_op3_cmp (dst, src1, src2, BITSET_OP_AND);
1220 lbitset_and (bitset dst, bitset src1, bitset src2)
1222 lbitset_and_cmp (dst, src1, src2);
1227 lbitset_andn_cmp (bitset dst, bitset src1, bitset src2)
1230 lbitset_elt *selt2 = LBITSET_HEAD (src2);
1244 return lbitset_op3_cmp (dst, src1, src2, BITSET_OP_ANDN)
[all...] |
| /external/clang/test/CodeGenCXX/ |
| debug-info-line.cpp | 87 int src2();
90 src1())[src2()];
96 int src2();
99 src1)[src2()];
105 int src2();
108 src1)[src2()];
|
| /external/llvm/test/CodeGen/X86/ |
| widen_shuffle-1.ll | 6 define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
16 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
17 %val = fadd <3 x float> %x, %src2
24 define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
35 %x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
36 %val = fadd <3 x float> %x, %src2
|
