| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_Interpolate_Chroma_s.s | 140 MUL BACoeff, dxEightMinusdx, EightMinusdy
141 MUL DCCoeff, dxEightMinusdx, dy
|
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s | 190 MUL alpha0, alpha0, t4
191 MUL beta0, beta0, t4
192 MUL alpha1, alpha1, t4
193 MUL beta1, beta1, t4
|
| omxVCM4P10_PredictIntra_16x16_s.s | 178 MUL tVal6, tVal6, r0x01010101 ;// replicate the val in all the bytes
180 MUL tVal7, tVal7, r0x01010101 ;// replicate the val in all the bytes
186 MUL tVal8, tVal8, r0x01010101 ;// replicate the val in all the bytes
189 MUL tVal9, tVal9, r0x01010101 ;// replicate the val in all the bytes
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/comm/src/ |
| omxVCCOMM_ExpandFrame_I_s.s | 88 MUL Offset, iExpandPels, iPlaneStep ;// E*Step
90 MUL Temp, iPlaneStep, Temp ;// (H-1)*Step
|
| /frameworks/compile/mclinker/include/mcld/Script/ |
| Operator.h | 36 MUL = 4,
163 Operator& Operator::create<Operator::MUL>();
|
| /frameworks/compile/mclinker/lib/Script/ |
| Operator.cpp | 161 Operator& Operator::create<Operator::MUL>() {
162 static BinaryOp<Operator::MUL> op;
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| Norm_Corr_opt.s | 169 MUL r12, r6, r11
208 MUL r14, r11, r8
216 MUL r14, r11, r8
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Norm_Corr_neon.s | 209 MUL r12, r6, r11
247 MUL r14, r11, r8
255 MUL r14, r11, r8
|
| syn_filt_neon.s | 67 MUL r12, r6, r5 @ L_tmp = x[i] * a0
|
| /external/deqp/framework/randomshaders/ |
| rsgToken.hpp | 66 MUL,
|
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 186 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
[all...] |
| /external/llvm/test/MC/ARM/ |
| mul-v4.s | 1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
5 @ ARMV4: mul r0, r1, r2 @ encoding: [0x91,0x02,0x00,0xe0]
9 mul r0, r1, r2 label
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_opcode_tmp.h | 50 OP12(MUL)
|
| /external/tremolo/Tremolo/ |
| floor1LARM.s | 57 MUL r5, r4, r5 @ r5 = MULT31_SHIFT15
|
| /external/v8/src/mips/ |
| constants-mips.cc | 262 case MUL:
|
| /external/v8/src/mips64/ |
| constants-mips64.cc | 279 case MUL:
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 238 ISD = ISD::MUL;
252 { ISD::SHL, MVT::v4i32, 2*5 }, // We optimized this using mul.
292 { ISD::MUL, MVT::v16i16, 4 },
293 { ISD::MUL, MVT::v8i32, 4 },
303 { ISD::MUL, MVT::v4i64, 18 },
314 ISD = ISD::MUL;
325 { ISD::MUL, MVT::v2i64, 9 },
326 { ISD::MUL, MVT::v4i64, 9 },
332 // Special lowering of v4i32 mul on sse2, sse3: Lower v4i32 mul as 2x shuffle
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| Rops.java | 244 new Rop(RegOps.MUL, Type.INT, StdTypeList.INT_INT, "mul-int");
248 new Rop(RegOps.MUL, Type.LONG, StdTypeList.LONG_LONG, "mul-long");
252 new Rop(RegOps.MUL, Type.FLOAT, StdTypeList.FLOAT_FLOAT, "mul-float");
256 new Rop(RegOps.MUL, Type.DOUBLE, StdTypeList.DOUBLE_DOUBLE,
257 Rop.BRANCH_NONE, "mul-double");
405 new Rop(RegOps.MUL, Type.INT, StdTypeList.INT, "mul-const-int")
[all...] |
| /dalvik/dx/src/com/android/dx/rop/code/ |
| Rops.java | 244 new Rop(RegOps.MUL, Type.INT, StdTypeList.INT_INT, "mul-int");
248 new Rop(RegOps.MUL, Type.LONG, StdTypeList.LONG_LONG, "mul-long");
252 new Rop(RegOps.MUL, Type.FLOAT, StdTypeList.FLOAT_FLOAT, "mul-float");
256 new Rop(RegOps.MUL, Type.DOUBLE, StdTypeList.DOUBLE_DOUBLE,
257 Rop.BRANCH_NONE, "mul-double");
405 new Rop(RegOps.MUL, Type.INT, StdTypeList.INT, "mul-const-int")
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/rop/code/ |
| Rops.java | 244 new Rop(RegOps.MUL, Type.INT, StdTypeList.INT_INT, "mul-int");
248 new Rop(RegOps.MUL, Type.LONG, StdTypeList.LONG_LONG, "mul-long");
252 new Rop(RegOps.MUL, Type.FLOAT, StdTypeList.FLOAT_FLOAT, "mul-float");
256 new Rop(RegOps.MUL, Type.DOUBLE, StdTypeList.DOUBLE_DOUBLE,
257 Rop.BRANCH_NONE, "mul-double");
405 new Rop(RegOps.MUL, Type.INT, StdTypeList.INT, "mul-const-int")
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_sao_edge_offset_class0_chroma.s | 97 MUL r4,r4,r1 @(ht - 1) * src_strd
154 MUL r14,r14,r1 @(ht - row) * src_strd
248 MUL r14,r14,r1 @II (ht - row) * src_strd
327 MUL r14,r14,r1 @(ht - row) * 2 * src_strd
403 MUL r14,r14,r1 @II (ht - row) * 2 * src_strd
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| /external/webp/src/dsp/ |
| dec_sse2.c | 85 // c = MUL(in1, K2) - MUL(in3, K1) = MUL(in1, k2) - MUL(in3, k1) + in1 - in3
91 // d = MUL(in1, K1) + MUL(in3, K2) = MUL(in1, k1) + MUL(in3, k2) + in1 + in3
143 // c = MUL(T1, K2) - MUL(T3, K1) = MUL(T1, k2) - MUL(T3, k1) + T1 - T
[all...] |
| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 12 MUL, MULT, MULTU, MOVN,
236 case MUL:
240 TEST1("mul $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerProxy.cpp | 169 void ARMAssemblerProxy::MUL(int cc, int s, int Rd, int Rm, int Rs) {
170 mTarget->MUL(cc, s, Rd, Rm, Rs);
|
