| /external/llvm/lib/Target/R600/ |
| SIRegisterInfo.cpp | 334 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
346 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
349 static const TargetRegisterClass *BaseClasses[] = {
362 for (const TargetRegisterClass *BaseClass : BaseClasses) {
370 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
379 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
380 const TargetRegisterClass *SRC) const {
399 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
400 const TargetRegisterClass *RC, unsigned SubIdx) const {
414 const TargetRegisterClass *SubRC
[all...] |
| SILowerI1Copies.cpp | 90 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
106 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
107 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
|
| AMDGPUInstrInfo.cpp | 95 const TargetRegisterClass *RC,
104 const TargetRegisterClass *RC,
259 AMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
285 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
|
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 41 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
46 const TargetRegisterClass *
48 const TargetRegisterClass *RC,
50 const TargetRegisterClass *OldRC = getRegClass(Reg);
53 const TargetRegisterClass *NewRC =
66 const TargetRegisterClass *OldRC = getRegClass(Reg);
67 const TargetRegisterClass *NewRC =
92 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
400 const TargetRegisterClass &TRC = *getRegClass(Reg);
|
| RegisterClassInfo.cpp | 79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
134 if (const TargetRegisterClass *Super =
157 const TargetRegisterClass *RC = nullptr;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXCopy.cpp | 57 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
99 const TargetRegisterClass *SrcRC =
122 const TargetRegisterClass *DstRC =
|
| PPCInstrInfo.h | 73 const TargetRegisterClass *RC,
78 const TargetRegisterClass *RC,
166 const TargetRegisterClass *RC,
172 const TargetRegisterClass *RC,
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| PPCRegisterInfo.cpp | 85 const TargetRegisterClass *
250 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
257 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
291 const TargetRegisterClass *
292 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
352 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
353 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
451 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
452 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
496 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass
[all...] |
| PPCFastISel.cpp | 115 const TargetRegisterClass *RC,
119 const TargetRegisterClass *RC,
122 const TargetRegisterClass *RC,
153 const TargetRegisterClass *RC, bool IsZExt = true,
165 const TargetRegisterClass *RC);
167 const TargetRegisterClass *RC);
433 const TargetRegisterClass *RC,
445 const TargetRegisterClass *UseRC =
576 const TargetRegisterClass *RC =
592 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUInstrInfo.h | 81 const TargetRegisterClass *RC,
86 const TargetRegisterClass *RC,
122 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 54 const TargetRegisterClass *RC,
61 const TargetRegisterClass *RC,
|
| Mips16RegisterInfo.cpp | 64 const TargetRegisterClass *RC,
73 const TargetRegisterClass *
|
| MipsSEFrameLowering.cpp | 155 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
170 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
188 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
213 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
245 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
294 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
295 const TargetRegisterClass *RC2 =
348 const TargetRegisterClass *RC =
350 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
476 const TargetRegisterClass *RC = STI.isABI_N64()
[all...] |
| MipsSERegisterInfo.cpp | 57 const TargetRegisterClass *
171 const TargetRegisterClass *RC =
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 86 const TargetRegisterClass *RC,
91 const TargetRegisterClass *RC,
97 const TargetRegisterClass *RC,
102 const TargetRegisterClass *RC,
|
| HexagonFrameLowering.cpp | 249 const TargetRegisterClass* SuperRegClass = nullptr;
266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
303 const TargetRegisterClass* SuperRegClass = nullptr;
320 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 277 const TargetRegisterClass *RC,
282 const TargetRegisterClass *RC,
290 const TargetRegisterClass *RC,
295 const TargetRegisterClass *RC,
374 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
|
| X86RegisterInfo.cpp | 99 const TargetRegisterClass *
100 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
111 const TargetRegisterClass *
112 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
113 const TargetRegisterClass *B,
124 const TargetRegisterClass *
125 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
138 const TargetRegisterClass *Super = RC;
139 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
163 const TargetRegisterClass *
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 39 class TargetRegisterClass;
65 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID,
208 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
640 const TargetRegisterClass *RC,
653 const TargetRegisterClass *RC,
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 103 const TargetRegisterClass *UseRC = nullptr;
133 const TargetRegisterClass *RC = nullptr;
141 const TargetRegisterClass *ComRC =
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
220 const TargetRegisterClass *RC =
227 const TargetRegisterClass *VTRC =
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
292 const TargetRegisterClass *RC =
333 const TargetRegisterClass *DstRC = nullptr;
442 const TargetRegisterClass *VRC = MRI->getRegClass(VReg)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 151 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
152 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
159 const TargetRegisterClass *
160 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
162 const TargetRegisterClass *Super = RC;
163 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
180 const TargetRegisterClass *
186 const TargetRegisterClass *
187 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
194 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC
[all...] |
| Thumb1InstrInfo.cpp | 73 const TargetRegisterClass *RC,
101 const TargetRegisterClass *RC,
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 39 class TargetRegisterClass;
[all...] |
| MachineRegisterInfo.h | 62 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
187 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
580 const TargetRegisterClass *getRegClass(unsigned Reg) const {
586 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
595 const TargetRegisterClass *constrainRegClass(unsigned Reg,
596 const TargetRegisterClass *RC,
612 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.cpp | 48 const TargetRegisterClass *RC,
66 const TargetRegisterClass *RC,
|
