| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.h | 100 int getMoveF64ViaSpillFI(const TargetRegisterClass *RC);
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| MipsRegisterInfo.cpp | 50 const TargetRegisterClass *
58 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
142 typedef TargetRegisterClass::const_iterator RegIter;
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| /external/llvm/lib/Target/R600/ |
| R600MachineScheduler.h | 87 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
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| SIInstrInfo.cpp | 449 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
465 const TargetRegisterClass *RC,
518 const TargetRegisterClass *RC,
885 SIInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
[all...] |
| SIFoldOperands.cpp | 216 const TargetRegisterClass *UseRC
240 const TargetRegisterClass *DestRC
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| SIISelLowering.h | 103 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
117 std::pair<unsigned, const TargetRegisterClass *> getRegForInlineAsmConstraint(
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 178 const TargetRegisterClass *RC,
183 const TargetRegisterClass *RC,
212 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
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| /external/llvm/lib/CodeGen/ |
| RegisterScavenging.cpp | 264 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
265 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
277 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
279 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
367 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
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| PeepholeOptimizer.cpp | 332 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
429 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
512 const TargetRegisterClass *DefRC,
514 const TargetRegisterClass *SrcRC,
552 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
577 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
[all...] |
| CalcSpillWeights.cpp | 64 const TargetRegisterClass *rc = mri.getRegClass(reg);
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| ExecutionDepsFix.cpp | 136 const TargetRegisterClass *const RC;
161 ExeDepsFix(const TargetRegisterClass *rc)
736 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
804 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
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| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 61 class TargetRegisterClass;
364 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
365 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
377 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
378 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| VirtRegMap.h | 64 unsigned createSpillSlot(const TargetRegisterClass *RC);
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| Passes.h | 31 class TargetRegisterClass;
593 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
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| ScheduleDAG.h | 40 class TargetRegisterClass;
320 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
321 const TargetRegisterClass *CopySrcRC;
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| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 146 const TargetRegisterClass *
152 const TargetRegisterClass *
153 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
416 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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| AArch64InstrInfo.h | 123 const TargetRegisterClass *RC,
128 int FrameIndex, const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 78 const TargetRegisterClass* const*
80 static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
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| HexagonVLIWPacketizer.cpp | 147 const TargetRegisterClass* RC);
151 const TargetRegisterClass *RC);
339 const TargetRegisterClass* RC = QRI->getMinimalPhysRegClass(DepReg);
430 const TargetRegisterClass* RC) {
553 const TargetRegisterClass* PacketRC = QII->getRegClass(MCID, 0, QRI, MF);
604 const TargetRegisterClass* predRegClass = nullptr;
744 MachineBasicBlock::iterator &MII, const TargetRegisterClass *RC) {
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.cpp | 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 264 const TargetRegisterClass *RC = &X86::VR256RegClass;
265 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end(); i != e;
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| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 79 const TargetRegisterClass *TRC);
103 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
139 const TargetRegisterClass *TRC) {
281 const TargetRegisterClass *TRC =
453 const TargetRegisterClass *TRC) {
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| ARMFastISel.cpp | 109 const TargetRegisterClass *RC,
112 const TargetRegisterClass *RC,
116 const TargetRegisterClass *RC,
121 const TargetRegisterClass *RC,
125 const TargetRegisterClass *RC,
130 const TargetRegisterClass *RC,
287 const TargetRegisterClass *RC,
309 const TargetRegisterClass *RC,
337 const TargetRegisterClass *RC,
369 const TargetRegisterClass *RC
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| ResourcePriorityQueue.cpp | 369 const TargetRegisterClass *RC = *I;
376 const TargetRegisterClass *RC = *I;
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
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