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  /external/libvpx/libvpx/vp8/common/ppc/
filter_bilinear_altivec.asm 23 .macro load_vfilter V0, V1
24 load_c \V0, vfilter_b, r6, r9, r10
87 vsrh v24, v24, v19 ;# divide v0, v1 by 128
181 hfilter_8 v0, 1
199 load_and_align_8 v0, 1
212 vfilter_16 v0, v1
219 stvx v0, 0, r1
266 hfilter_8 v0, 1
284 load_and_align_8 v0, 1
297 vfilter_16 v0, v
    [all...]
variance_subpixel_altivec.asm 24 .macro load_vfilter V0, V1
25 load_c \V0, vfilter_b, r6, r12, r10
102 vsrh v24, v24, v19 ;# divide v0, v1 by 128
208 hfilter_8 v0, v10, v11, 1
226 load_and_align_16 v0, r3, r4, 1
239 vfilter_16 v0, v1
255 vmrghb v0, v0, v1
263 vperm v0, v0, v1, v1
    [all...]
filter_altivec.asm 23 .macro load_hfilter V0, V1
24 load_c \V0, HFilter, r5, r9, r10
32 load_c v0, VFilter, r6, r3, r10
38 vspltb v1, v0, 1
39 vspltb v2, v0, 2
40 vspltb v3, v0, 3
41 vspltb v4, v0, 4
42 vspltb v5, v0, 5
43 vspltb v0, v0,
    [all...]
  /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/ppc/
filter_bilinear_altivec.asm 23 .macro load_vfilter V0, V1
24 load_c \V0, vfilter_b, r6, r9, r10
87 vsrh v24, v24, v19 ;# divide v0, v1 by 128
181 hfilter_8 v0, 1
199 load_and_align_8 v0, 1
212 vfilter_16 v0, v1
219 stvx v0, 0, r1
266 hfilter_8 v0, 1
284 load_and_align_8 v0, 1
297 vfilter_16 v0, v
    [all...]
variance_subpixel_altivec.asm 24 .macro load_vfilter V0, V1
25 load_c \V0, vfilter_b, r6, r12, r10
102 vsrh v24, v24, v19 ;# divide v0, v1 by 128
208 hfilter_8 v0, v10, v11, 1
226 load_and_align_16 v0, r3, r4, 1
239 vfilter_16 v0, v1
255 vmrghb v0, v0, v1
263 vperm v0, v0, v1, v1
    [all...]
filter_altivec.asm 23 .macro load_hfilter V0, V1
24 load_c \V0, HFilter, r5, r9, r10
32 load_c v0, VFilter, r6, r3, r10
38 vspltb v1, v0, 1
39 vspltb v2, v0, 2
40 vspltb v3, v0, 3
41 vspltb v4, v0, 4
42 vspltb v5, v0, 5
43 vspltb v0, v0,
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonISelLowering.cpp     [all...]
  /external/mesa3d/src/mesa/drivers/dri/i915/
i830_vtbl.c 51 #define EMIT_ATTR( ATTR, STYLE, V0 ) \
56 v0 |= V0; \
84 GLuint v0 = _3DSTATE_VFT0_CMD; local
172 v0 |= VFT0_TEX_COUNT(count);
178 if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
197 i830->state.Ctx[I830_CTXREG_VF] = v0;
  /external/mesa3d/src/mesa/main/
texcompress_fxt1.c 252 #define MAKEIVEC(NV, NC, IV, B, V0, V1) \
259 IV[i] = (V1[i] - V0[i]) * F(i); \
266 B -= IV[i] * V0[i]; \
    [all...]
  /external/llvm/lib/Target/Mips/
Mips16InstrInfo.cpp 221 adjustStackPtrBig(SP, -Remainder, MBB, I, Mips::V0, Mips::V1);
Mips16ISelLowering.cpp 502 unsigned V0Reg = Mips::V0;
MipsISelLowering.cpp 764 // (add v0, (add v1, abs_lo(tjt))) => (add (add v0, v1), abs_lo(tjt))
    [all...]
  /external/llvm/lib/Target/PowerPC/Disassembler/
PPCDisassembler.cpp 84 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
  /external/llvm/lib/Transforms/InstCombine/
InstCombineCalls.cpp 281 Value *V0 = LowInputSelect ? II.getArgOperand(1) : II.getArgOperand(0);
285 V0 = LowHalfZero ? ZeroVector : V0;
299 return Builder.CreateShuffleVector(V0, V1, ShuffleMask);
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
LegalizeIntegerTypes.cpp     [all...]
  /external/mesa3d/src/mesa/vbo/
vbo_exec_api.c 405 #define ATTR( A, N, T, V0, V1, V2, V3 ) \
417 if (N>0) dest[0] = V0; \
    [all...]
vbo_save_api.c 697 #define ATTR(A, N, T, V0, V1, V2, V3) \
706 if (N>0) dest[0] = V0; \
    [all...]
  /external/deqp/framework/common/
tcuCompressedTexture.cpp     [all...]
  /frameworks/base/media/tests/contents/media_api/music/
test_amr_ietf.amr 18 ??zF????/L9??-~PJB(?<z_1?&??????|D?p?B????5???<m!???C?|L2?{D?g???5??s???p<??????????f??!)?XH<(??h?p<?? AF8?)J7???z x;?!?? '?p<.??s????????? ??n4R?{??<??$???R?2-?H????O??.?`TQ?0<F5o?i?)v0
253 ??<?r??p!?|JKo?,U??R?JK?&8?? ]?<TpM?z????U!4K?F?l????p?v!@<?^I?*??~????$/?P??;v0?h??@<??U????5??FTe???D?????84? <?z$/???K4y?g???
289 ?<?!>{Z 4?<f]v0??;A@??d?w(A? <??q ]??:R|5???g ?o{}???Z?sP<SFzz???3???OP??zK^?|[??xF <EĢ??`???k???|.???] ?A?`?<????>??
343 ?O??????T??0C,\%?<?-k???? 5?e?V?1???!???,~K?v?<?d'?S ???:??h??+V0-????I~@<8 7?&=???[?^5{?O"-'?/?? ~??<??'?{?A?????Q????\?0?V?B(_
402 ;???E?";??$jnC?<?j???p??HO?<(dF-g?+?????S???????{@<?p>?/??*??K??*O?9#??`V?^`<B>??[??z??zS?W=v0?2'?6 ??GoI0<Ri?W?s???G?rR?^??dy(y?a?/0<DL G??a???&?????B???yWd?KDQ0<RhG?@?!????SC??.g ????V?K?/?<DTO??????Ej[??5?%?<q$?=????<B^??.??(??U?iZ ?K,$?.R\?p<>#G?#??u??#?H?o? _????i??<
    [all...]
  /external/llvm/lib/Transforms/Vectorize/
SLPVectorizer.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
    [all...]
  /art/compiler/optimizing/
code_generator_mips64.cc 54 return Location::RegisterLocation(V0);
454 // Else, spill V0 (arbitrary choice) and use it as a scratch register (it will be
456 ScratchRegisterScope ensure_scratch(this, TMP, V0, codegen_->GetNumberOfCoreRegisters());
457 // If V0 spills onto the stack, SP-relative offsets need to be adjusted.
    [all...]
  /external/llvm/lib/Target/X86/
X86ISelLowering.cpp     [all...]
  /external/llvm/lib/Target/PowerPC/AsmParser/
PPCAsmParser.cpp 88 PPC::V0, PPC::V1, PPC::V2, PPC::V3,
    [all...]
  /external/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp     [all...]

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