| /external/libvpx/libvpx/vp9/common/ |
| vp9_common_data.c | 157 {12, 8 }, // 16X32 - {0b1100, 0b1000}
158 {8, 12}, // 32X16 - {0b1000, 0b1100}
159 {8, 8 }, // 32X32 - {0b1000, 0b1000}
160 {8, 0 }, // 32X64 - {0b1000, 0b0000}
161 {0, 8 }, // 64X32 - {0b0000, 0b1000}
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/ |
| vp9_common_data.c | 150 {12, 8 }, // 16X32 - {0b1100, 0b1000}
151 {8, 12}, // 32X16 - {0b1000, 0b1100}
152 {8, 8 }, // 32X32 - {0b1000, 0b1000}
153 {8, 0 }, // 32X64 - {0b1000, 0b0000}
154 {0, 8 }, // 64X32 - {0b0000, 0b1000}
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfoV5.td | 134 let IClass = 0b1000;
539 let IClass = 0b1000;
558 let IClass = 0b1000;
577 let IClass = 0b1000;
579 let Inst{27-24} = 0b1000;
597 let IClass = 0b1000;
677 let IClass = 0b1000;
813 let IClass = 0b1000;
842 let IClass = 0b1000;
870 let IClass = 0b1000;
[all...] |
| HexagonInstrInfo.td | 631 let Inst{27-24} = 0b1000;
[all...] |
| HexagonInstrInfoV3.td | 204 let Inst{27-24} = 0b1000;
|
| HexagonInstrInfoV4.td | 416 def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
472 def L4_loadrb_ur : T_LoadAbsReg<"memb", "LDrib", IntRegs, 0b1000>;
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrAliases.td | 247 defm : int_cond_alias<"a", 0b1000>;
265 defm : fp_cond_alias<"n", 0b1000>;
|
| /bionic/libc/arch-arm64/denver64/bionic/ |
| memset.S | 238 ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */
|
| /bionic/libc/arch-arm64/generic/bionic/ |
| memset.S | 211 ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */
|
| /external/libnfc-nci/halimpl/bcm2079x/gki/common/ |
| gki_common.h | 33 #define TASK_SUSPEND 8 /* b1000 */
|
| /external/libnfc-nci/src/gki/common/ |
| gki_common.h | 33 #define TASK_SUSPEND 8 /* b1000 */
|
| /packages/apps/Launcher3/src/com/android/launcher3/ |
| ShortcutInfo.java | 63 public static final int FLAG_RESTORE_STARTED = 8; //0B1000;
|
| /system/core/libcutils/arch-arm64/ |
| android_memset.S | 186 ccmp tmp1, zva_len_x, #8, ge /* NZCV=0b1000 */
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | 748 def S : ASuInp<0b11101, 0b11, 0b1000, 0b01, 0,
755 def D : ADuInp<0b11101, 0b11, 0b1000, 0b01, 0,
[all...] |
| ARMInstrNEON.td | [all...] |
| ARMInstrThumb.td | 641 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
696 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
[all...] |
| ARMInstrThumb2.td | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_blorp_blit.cpp | 455 * | (A & 0b1000) >> 2
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsMSAInstrInfo.td | 711 class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
712 class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
[all...] |
| /art/compiler/utils/arm/ |
| assembler_thumb2.cc | 812 case ADD: thumb_opcode = 8U /* 0b1000 */; break;
819 case CMN: thumb_opcode = 8U /* 0b1000 */; set_cc = true; rd = PC; break;
981 case TST: thumb_opcode = 8U /* 0b1000 */; CHECK(!use_immediate); break;
1080 (static_cast<uint32_t>(rd) & 8U /* 0b1000 */) << 1);
[all...] |
| assembler_arm.cc | 249 if ((PU1W & 8U /* 0b1000 */) == 0) {
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-ia32.cc | 523 // The mask should be 0b1000.
|
| test-assembler-x64.cc | 667 // The mask should be 0b1000.
|
| /art/disassembler/ |
| disassembler_x86.cc | 63 constexpr uint8_t REX_W = 8U /* 0b1000 */;
[all...] |
| /external/v8/src/arm64/ |
| disasm-arm64.cc | [all...] |
