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      1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file describes the Hexagon V3 instructions in TableGen format.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
     15            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
     16 
     17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
     18            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
     19 
     20 //===----------------------------------------------------------------------===//
     21 // J +
     22 //===----------------------------------------------------------------------===//
     23 // Call subroutine.
     24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
     25     isExtended = 0, isExtendable = 1, opExtendable = 0,
     26     isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
     27 class T_Call<string ExtStr>
     28   : JInst<(outs), (ins calltarget:$dst),
     29       "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
     30   let BaseOpcode = "call";
     31   bits<24> dst;
     32 
     33   let IClass = 0b0101;
     34   let Inst{27-25} = 0b101;
     35   let Inst{24-16,13-1} = dst{23-2};
     36   let Inst{0} = 0b0;
     37 }
     38 
     39 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
     40     isExtended = 0, isExtendable = 1, opExtendable = 1,
     41     isExtentSigned = 1, opExtentBits = 17, opExtentAlign = 2 in
     42 class T_CallPred<bit IfTrue, string ExtStr>
     43   : JInst<(outs), (ins PredRegs:$Pu, calltarget:$dst),
     44       CondStr<"$Pu", IfTrue, 0>.S # "call " # ExtStr # "$dst",
     45       [], "", J_tc_2early_SLOT23> {
     46   let BaseOpcode = "call";
     47   let isPredicatedFalse = !if(IfTrue,0,1);
     48   bits<2> Pu;
     49   bits<17> dst;
     50 
     51   let IClass = 0b0101;
     52   let Inst{27-24} = 0b1101;
     53   let Inst{23-22,20-16,13,7-1} = dst{16-2};
     54   let Inst{21} = !if(IfTrue,0,1);
     55   let Inst{11} = 0b0;
     56   let Inst{9-8} = Pu;
     57 }
     58 
     59 multiclass T_Calls<string ExtStr> {
     60   def NAME : T_Call<ExtStr>;
     61   def t    : T_CallPred<1, ExtStr>;
     62   def f    : T_CallPred<0, ExtStr>;
     63 }
     64 
     65 defm J2_call: T_Calls<"">, PredRel;
     66 
     67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
     68 def CALLv3nr :  T_Call<"">, PredRel;
     69 
     70 //===----------------------------------------------------------------------===//
     71 // J -
     72 //===----------------------------------------------------------------------===//
     73 
     74 
     75 //===----------------------------------------------------------------------===//
     76 // JR +
     77 //===----------------------------------------------------------------------===//
     78 // Call subroutine from register.
     79 
     80 let isCodeGenOnly = 1, Defs = VolatileV3.Regs in {
     81   def CALLRv3nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
     82 }
     83 
     84 //===----------------------------------------------------------------------===//
     85 // JR -
     86 //===----------------------------------------------------------------------===//
     87 
     88 //===----------------------------------------------------------------------===//
     89 // ALU64/ALU +
     90 //===----------------------------------------------------------------------===//
     91 
     92 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23 in
     93 def A2_addpsat : T_ALU64_arith<"add", 0b011, 0b101, 1, 0, 1>;
     94 
     95 class T_ALU64_addsp_hl<string suffix, bits<3> MinOp>
     96   : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
     97 
     98 def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
     99 def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
    100 
    101 let hasSideEffects = 0, isAsmParserOnly = 1 in
    102 def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
    103   (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
    104   [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
    105                                         (i64 DoubleRegs:$Rt))))],
    106   "", ALU64_tc_1_SLOT23>;
    107 
    108 
    109 let hasSideEffects = 0 in
    110 class T_XTYPE_MIN_MAX_P<bit isMax, bit isUnsigned>
    111   : ALU64Inst<(outs DoubleRegs:$Rd), (ins DoubleRegs:$Rt, DoubleRegs:$Rs),
    112   "$Rd = "#!if(isMax,"max","min")#!if(isUnsigned,"u","")
    113           #"($Rt, $Rs)", [], "", ALU64_tc_2_SLOT23> {
    114   bits<5> Rd;
    115   bits<5> Rs;
    116   bits<5> Rt;
    117 
    118   let IClass = 0b1101;
    119 
    120   let Inst{27-23} = 0b00111;
    121   let Inst{22-21} = !if(isMax, 0b10, 0b01);
    122   let Inst{20-16} = !if(isMax, Rt, Rs);
    123   let Inst{12-8} = !if(isMax, Rs, Rt);
    124   let Inst{7} = 0b1;
    125   let Inst{6} = !if(isMax, 0b0, 0b1);
    126   let Inst{5} = isUnsigned;
    127   let Inst{4-0} = Rd;
    128 }
    129 
    130 def A2_minp  : T_XTYPE_MIN_MAX_P<0, 0>;
    131 def A2_minup : T_XTYPE_MIN_MAX_P<0, 1>;
    132 def A2_maxp  : T_XTYPE_MIN_MAX_P<1, 0>;
    133 def A2_maxup : T_XTYPE_MIN_MAX_P<1, 1>;
    134 
    135 multiclass MinMax_pats_p<PatFrag Op, InstHexagon Inst, InstHexagon SwapInst> {
    136   defm: T_MinMax_pats<Op, DoubleRegs, i64, Inst, SwapInst>;
    137 }
    138 
    139 let AddedComplexity = 200 in {
    140   defm: MinMax_pats_p<setge,  A2_maxp,  A2_minp>;
    141   defm: MinMax_pats_p<setgt,  A2_maxp,  A2_minp>;
    142   defm: MinMax_pats_p<setle,  A2_minp,  A2_maxp>;
    143   defm: MinMax_pats_p<setlt,  A2_minp,  A2_maxp>;
    144   defm: MinMax_pats_p<setuge, A2_maxup, A2_minup>;
    145   defm: MinMax_pats_p<setugt, A2_maxup, A2_minup>;
    146   defm: MinMax_pats_p<setule, A2_minup, A2_maxup>;
    147   defm: MinMax_pats_p<setult, A2_minup, A2_maxup>;
    148 }
    149 
    150 //===----------------------------------------------------------------------===//
    151 // ALU64/ALU -
    152 //===----------------------------------------------------------------------===//
    153 
    154 
    155 
    156 
    157 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
    158 //      (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>;
    159 
    160 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
    161 //      (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>;
    162 
    163 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
    164 //      (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>;
    165 
    166 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
    167 //      (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
    168 
    169 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
    170 //      (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>;
    171 
    172 // Map call instruction
    173 def : Pat<(callv3 (i32 IntRegs:$dst)),
    174       (J2_callr (i32 IntRegs:$dst))>;
    175 def : Pat<(callv3 tglobaladdr:$dst),
    176       (J2_call tglobaladdr:$dst)>;
    177 def : Pat<(callv3 texternalsym:$dst),
    178       (J2_call texternalsym:$dst)>;
    179 def : Pat<(callv3 tglobaltlsaddr:$dst),
    180       (J2_call tglobaltlsaddr:$dst)>;
    181 
    182 def : Pat<(callv3nr (i32 IntRegs:$dst)),
    183       (CALLRv3nr (i32 IntRegs:$dst))>;
    184 def : Pat<(callv3nr tglobaladdr:$dst),
    185       (CALLv3nr tglobaladdr:$dst)>;
    186 def : Pat<(callv3nr texternalsym:$dst),
    187       (CALLv3nr texternalsym:$dst)>;
    188 
    189 //===----------------------------------------------------------------------===//
    190 // :raw form of vrcmpys:hi/lo insns
    191 //===----------------------------------------------------------------------===//
    192 // Vector reduce complex multiply by scalar.
    193 let Defs = [USR_OVF], hasSideEffects = 0 in
    194 class T_vrcmpRaw<string HiLo, bits<3>MajOp>:
    195   MInst<(outs DoubleRegs:$Rdd),
    196          (ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
    197          "$Rdd = vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, []> {
    198     bits<5> Rdd;
    199     bits<5> Rss;
    200     bits<5> Rtt;
    201 
    202     let IClass = 0b1110;
    203 
    204     let Inst{27-24} = 0b1000;
    205     let Inst{23-21} = MajOp;
    206     let Inst{20-16} = Rss;
    207     let Inst{12-8}  = Rtt;
    208     let Inst{7-5}   = 0b100;
    209     let Inst{4-0}   = Rdd;
    210 }
    211 
    212 def M2_vrcmpys_s1_h: T_vrcmpRaw<"hi", 0b101>;
    213 def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
    214 
    215 // Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
    216 let hasSideEffects = 0, isAsmParserOnly = 1 in
    217 def M2_vrcmpys_s1
    218  : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
    219  "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
    220 
    221 // Vector reduce complex multiply by scalar with accumulation.
    222 let Defs = [USR_OVF], hasSideEffects = 0 in
    223 class T_vrcmpys_acc<string HiLo, bits<3>MajOp>:
    224   MInst <(outs DoubleRegs:$Rxx),
    225          (ins DoubleRegs:$_src_, DoubleRegs:$Rss, DoubleRegs:$Rtt),
    226   "$Rxx += vrcmpys($Rss, $Rtt):<<1:sat:raw:"#HiLo, [],
    227   "$Rxx = $_src_"> {
    228     bits<5> Rxx;
    229     bits<5> Rss;
    230     bits<5> Rtt;
    231 
    232     let IClass = 0b1110;
    233 
    234     let Inst{27-24} = 0b1010;
    235     let Inst{23-21} = MajOp;
    236     let Inst{20-16} = Rss;
    237     let Inst{12-8}  = Rtt;
    238     let Inst{7-5}   = 0b100;
    239     let Inst{4-0}   = Rxx;
    240   }
    241 
    242 def M2_vrcmpys_acc_s1_h: T_vrcmpys_acc<"hi", 0b101>;
    243 def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
    244 
    245 // Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
    246 
    247 let isAsmParserOnly = 1 in
    248 def M2_vrcmpys_acc_s1
    249   : MInst <(outs DoubleRegs:$dst),
    250            (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
    251            "$dst += vrcmpys($src1, $src2):<<1:sat", [],
    252            "$dst2 = $dst">;
    253 
    254 def M2_vrcmpys_s1rp_h : T_MType_vrcmpy <"vrcmpys", 0b101, 0b110, 1>;
    255 def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
    256 
    257 // Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
    258 let isAsmParserOnly = 1 in
    259 def M2_vrcmpys_s1rp
    260   : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
    261   "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;
    262 
    263 
    264 // S2_cabacdecbin: Cabac decode bin.
    265 let Defs = [P0], isPredicateLate = 1, Itinerary = S_3op_tc_1_SLOT23 in
    266 def S2_cabacdecbin : T_S3op_64 < "decbin", 0b11, 0b110, 0>;
    267