| /external/llvm/test/TableGen/ |
| list-element-bitref.td | 10 def c0 : C<[0b0101, 0b1010]>;
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrVFP.td | 801 def VMOVRS : AVConv2I<0b11100001, 0b1010,
823 def VMOVSR : AVConv4I<0b11100000, 0b1010,
873 def VMOVRRS : AVConv3I<0b11000101, 0b1010,
[all...] |
| ARMInstrNEON.td | 680 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
717 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
725 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
[all...] |
| ARMInstrThumb.td | 308 let Inst{9-6} = 0b1010;
[all...] |
| ARMInstrInfo.td | [all...] |
| ARMInstrThumb2.td | [all...] |
| /external/clang/test/Lexer/ |
| cxx1y_digit_separators.cpp | 18 int e = 0'b1010; // expected-error {{digit 'b' in octal constant}}
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrAliases.td | 251 defm : int_cond_alias<"g", 0b1010>;
274 defm : fp_cond_alias<"ue", 0b1010>;
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.td | [all...] |
| HexagonInstrInfoV4.td | 421 def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
479 def L4_loadrh_ur : T_LoadAbsReg<"memh", "LDrih", IntRegs, 0b1010>;
535 let Inst{27-24} = 0b1010;
685 let IClass = 0b1010;
721 let IClass = 0b1010;
755 let IClass = 0b1010;
813 let IClass = 0b1010;
[all...] |
| HexagonInstrInfoV3.td | 234 let Inst{27-24} = 0b1010;
|
| /external/llvm/lib/Target/Mips/ |
| MipsMSAInstrInfo.td | [all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-thumbv7.txt | 277 # VLD1 multi-element, type=0b1010 align=0b11
|
| invalid-armv7.txt | 447 # VST1 multi-element, type == 0b1010, align == 0b11 -> undefined
|
| /art/compiler/utils/arm/ |
| assembler_thumb2.cc | 813 case ADC: thumb_opcode = 10U /* 0b1010 */; break;
992 thumb_opcode = 10U /* 0b1010 */;
[all...] |
| /external/clang/lib/Lex/ |
| LiteralSupport.cpp | 743 /// number (like '04') or a hex number ('0x123a') a binary number ('0b1010') or
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| AArch64InstrFormats.td | [all...] |
| /art/disassembler/ |
| disassembler_arm.cc | 90 case 10U /* 0b1010 */: os << "ishst"; break;
[all...] |
| /libcore/luni/src/test/java/libcore/java/lang/reflect/ |
| Annotations57649Test.java | [all...] |
