| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vecFold.ll | 53 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
54 %vaddhn2.i10 = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
55 ; CHECK: addhn.4h v0, v0, v1
67 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a0, <4 x i32> %a1) nounwind
70 ; CHECK: addhn.4h v0, v0, v1
126 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %b0, <4 x i32> %b1) nounwind
141 declare <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
|
| arm64-vadd.ll | 5 ;CHECK: addhn.8b
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
14 ;CHECK: addhn.4h
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
23 ;CHECK: addhn.2s
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
32 ;CHECK: addhn.8b
34 %vaddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
35 %vaddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind
42 ;CHECK: addhn.4
[all...] |
| arm64-neon-3vdiff.ll | 547 ; CHECK: addhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
557 ; CHECK: addhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
567 ; CHECK: addhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
577 ; CHECK: addhn {{v[0-9]+}}.8b, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
587 ; CHECK: addhn {{v[0-9]+}}.4h, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
597 ; CHECK: addhn {{v[0-9]+}}.2s, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
[all...] |
| /external/llvm/test/MC/AArch64/ |
| neon-3vdiff.s | 369 addhn v0.8b, v1.8h, v2.8h
370 addhn v0.4h, v1.4s, v2.4s
371 addhn v0.2s, v1.2d, v2.2d
373 // CHECK: addhn v0.8b, v1.8h, v2.8h // encoding: [0x20,0x40,0x22,0x0e]
374 // CHECK: addhn v0.4h, v1.4s, v2.4s // encoding: [0x20,0x40,0x62,0x0e]
375 // CHECK: addhn v0.2s, v1.2d, v2.2d // encoding: [0x20,0x40,0xa2,0x0e]
|
| arm64-advsimd.s | 39 addhn.8b v0, v0, v0
41 addhn.4h v0, v0, v0
43 addhn.2s v0, v0, v0
46 ; CHECK: addhn.8b v0, v0, v0 ; encoding: [0x00,0x40,0x20,0x0e]
48 ; CHECK: addhn.4h v0, v0, v0 ; encoding: [0x00,0x40,0x60,0x0e]
50 ; CHECK: addhn.2s v0, v0, v0 ; encoding: [0x00,0x40,0xa0,0x0e]
[all...] |
| neon-diagnostics.s | [all...] |
| /external/skia/src/opts/ |
| SkBlitRow_opts_arm_neon.cpp | 418 "addhn v20.8b, v22.8h, v20.8h \t\n"
427 "addhn v7.8b, v7.8h, v24.8h \t\n"
433 "addhn v6.8b, v6.8h, v19.8h \t\n"
[all...] |
| /external/llvm/test/MC/Disassembler/AArch64/ |
| arm64-advsimd.txt | 44 # CHECK: addhn.8b v0, v0, v0
46 # CHECK: addhn.4h v0, v0, v0
48 # CHECK: addhn.2s v0, v0, v0
[all...] |
| neon-instructions.txt | [all...] |
| /external/vixl/doc/ |
| supported-instructions.md | 1419 ### ADDHN ###
1423 void addhn(const VRegister& vd,
[all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.h | [all...] |
| disasm-a64.cc | [all...] |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| logic-a64.cc | 3303 LogicVRegister Simulator::addhn(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| /external/vixl/test/ |
| test-simulator-traces-a64.h | 79 #include "traces/a64/sim-addhn-2s-trace-a64.h"
80 #include "traces/a64/sim-addhn-4h-trace-a64.h"
81 #include "traces/a64/sim-addhn-8b-trace-a64.h"
[all...] |
| test-disasm-a64.cc | [all...] |
| test-simulator-a64.cc | [all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-intrinsics.c | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.c | [all...] |
| fp_and_simd.stdout.exp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
| /prebuilts/android-emulator/linux-x86_64/lib/gles_mesa/ |
| libGL.so | |
