1 VIXL Supported Instruction List 2 =============================== 3 4 This is a list of the AArch64 instructions supported by the VIXL assembler, 5 disassembler and simulator. The simulator may not support all floating point 6 operations to the precision required by AArch64 - please check the simulator 7 source code for details. 8 9 AArch64 integer instructions 10 ---------------------------- 11 12 ### ADC ### 13 14 Add with carry bit. 15 16 void adc(const Register& rd, 17 const Register& rn, 18 const Operand& operand) 19 20 21 ### ADCS ### 22 23 Add with carry bit and update status flags. 24 25 void adcs(const Register& rd, 26 const Register& rn, 27 const Operand& operand) 28 29 30 ### ADD ### 31 32 Add. 33 34 void add(const Register& rd, 35 const Register& rn, 36 const Operand& operand) 37 38 39 ### ADDS ### 40 41 Add and update status flags. 42 43 void adds(const Register& rd, 44 const Register& rn, 45 const Operand& operand) 46 47 48 ### ADR ### 49 50 Calculate the address of a PC offset. 51 52 void adr(const Register& rd, int imm21) 53 54 55 ### ADR ### 56 57 Calculate the address of a label. 58 59 void adr(const Register& rd, Label* label) 60 61 62 ### ADRP ### 63 64 Calculate the page address of a PC offset. 65 66 void adrp(const Register& rd, int imm21) 67 68 69 ### ADRP ### 70 71 Calculate the page address of a label. 72 73 void adrp(const Register& rd, Label* label) 74 75 76 ### AND ### 77 78 Bitwise and (A & B). 79 80 void and_(const Register& rd, 81 const Register& rn, 82 const Operand& operand) 83 84 85 ### ANDS ### 86 87 Bitwise and (A & B) and update status flags. 88 89 void ands(const Register& rd, 90 const Register& rn, 91 const Operand& operand) 92 93 94 ### ASR ### 95 96 Arithmetic shift right. 97 98 void asr(const Register& rd, const Register& rn, unsigned shift) 99 100 101 ### ASRV ### 102 103 Arithmetic shift right by variable. 104 105 void asrv(const Register& rd, const Register& rn, const Register& rm) 106 107 108 ### B ### 109 110 Conditional branch to PC offset. 111 112 void b(int imm19, Condition cond) 113 114 115 ### B ### 116 117 Conditional branch to label. 118 119 void b(Label* label, Condition cond) 120 121 122 ### B ### 123 124 Unconditional branch to PC offset. 125 126 void b(int imm26) 127 128 129 ### B ### 130 131 Unconditional branch to label. 132 133 void b(Label* label) 134 135 136 ### BFI ### 137 138 Bitfield insert. 139 140 void bfi(const Register& rd, 141 const Register& rn, 142 unsigned lsb, 143 unsigned width) 144 145 146 ### BFM ### 147 148 Bitfield move. 149 150 void bfm(const Register& rd, 151 const Register& rn, 152 unsigned immr, 153 unsigned imms) 154 155 156 ### BFXIL ### 157 158 Bitfield extract and insert low. 159 160 void bfxil(const Register& rd, 161 const Register& rn, 162 unsigned lsb, 163 unsigned width) 164 165 166 ### BIC ### 167 168 Bit clear (A & ~B). 169 170 void bic(const Register& rd, 171 const Register& rn, 172 const Operand& operand) 173 174 175 ### BICS ### 176 177 Bit clear (A & ~B) and update status flags. 178 179 void bics(const Register& rd, 180 const Register& rn, 181 const Operand& operand) 182 183 184 ### BL ### 185 186 Branch with link to PC offset. 187 188 void bl(int imm26) 189 190 191 ### BL ### 192 193 Branch with link to label. 194 195 void bl(Label* label) 196 197 198 ### BLR ### 199 200 Branch with link to register. 201 202 void blr(const Register& xn) 203 204 205 ### BR ### 206 207 Branch to register. 208 209 void br(const Register& xn) 210 211 212 ### BRK ### 213 214 Monitor debug-mode breakpoint. 215 216 void brk(int code) 217 218 219 ### CBNZ ### 220 221 Compare and branch to PC offset if not zero. 222 223 void cbnz(const Register& rt, int imm19) 224 225 226 ### CBNZ ### 227 228 Compare and branch to label if not zero. 229 230 void cbnz(const Register& rt, Label* label) 231 232 233 ### CBZ ### 234 235 Compare and branch to PC offset if zero. 236 237 void cbz(const Register& rt, int imm19) 238 239 240 ### CBZ ### 241 242 Compare and branch to label if zero. 243 244 void cbz(const Register& rt, Label* label) 245 246 247 ### CCMN ### 248 249 Conditional compare negative. 250 251 void ccmn(const Register& rn, 252 const Operand& operand, 253 StatusFlags nzcv, 254 Condition cond) 255 256 257 ### CCMP ### 258 259 Conditional compare. 260 261 void ccmp(const Register& rn, 262 const Operand& operand, 263 StatusFlags nzcv, 264 Condition cond) 265 266 267 ### CINC ### 268 269 Conditional increment: rd = cond ? rn + 1 : rn. 270 271 void cinc(const Register& rd, const Register& rn, Condition cond) 272 273 274 ### CINV ### 275 276 Conditional invert: rd = cond ? ~rn : rn. 277 278 void cinv(const Register& rd, const Register& rn, Condition cond) 279 280 281 ### CLREX ### 282 283 Clear exclusive monitor. 284 285 void clrex(int imm4 = 0xf) 286 287 288 ### CLS ### 289 290 Count leading sign bits. 291 292 void cls(const Register& rd, const Register& rn) 293 294 295 ### CLZ ### 296 297 Count leading zeroes. 298 299 void clz(const Register& rd, const Register& rn) 300 301 302 ### CMN ### 303 304 Compare negative. 305 306 void cmn(const Register& rn, const Operand& operand) 307 308 309 ### CMP ### 310 311 Compare. 312 313 void cmp(const Register& rn, const Operand& operand) 314 315 316 ### CNEG ### 317 318 Conditional negate: rd = cond ? -rn : rn. 319 320 void cneg(const Register& rd, const Register& rn, Condition cond) 321 322 323 ### CRC32B ### 324 325 CRC-32 checksum from byte. 326 327 void crc32b(const Register& rd, 328 const Register& rn, 329 const Register& rm) 330 331 332 ### CRC32CB ### 333 334 CRC-32 C checksum from byte. 335 336 void crc32cb(const Register& rd, 337 const Register& rn, 338 const Register& rm) 339 340 341 ### CRC32CH ### 342 343 CRC-32 C checksum from half-word. 344 345 void crc32ch(const Register& rd, 346 const Register& rn, 347 const Register& rm) 348 349 350 ### CRC32CW ### 351 352 CRC-32 C checksum from word. 353 354 void crc32cw(const Register& rd, 355 const Register& rn, 356 const Register& rm) 357 358 359 ### CRC32CX ### 360 361 CRC-32C checksum from double word. 362 363 void crc32cx(const Register& rd, 364 const Register& rn, 365 const Register& rm) 366 367 368 ### CRC32H ### 369 370 CRC-32 checksum from half-word. 371 372 void crc32h(const Register& rd, 373 const Register& rn, 374 const Register& rm) 375 376 377 ### CRC32W ### 378 379 CRC-32 checksum from word. 380 381 void crc32w(const Register& rd, 382 const Register& rn, 383 const Register& rm) 384 385 386 ### CRC32X ### 387 388 CRC-32 checksum from double word. 389 390 void crc32x(const Register& rd, 391 const Register& rn, 392 const Register& rm) 393 394 395 ### CSEL ### 396 397 Conditional select: rd = cond ? rn : rm. 398 399 void csel(const Register& rd, 400 const Register& rn, 401 const Register& rm, 402 Condition cond) 403 404 405 ### CSET ### 406 407 Conditional set: rd = cond ? 1 : 0. 408 409 void cset(const Register& rd, Condition cond) 410 411 412 ### CSETM ### 413 414 Conditional set mask: rd = cond ? -1 : 0. 415 416 void csetm(const Register& rd, Condition cond) 417 418 419 ### CSINC ### 420 421 Conditional select increment: rd = cond ? rn : rm + 1. 422 423 void csinc(const Register& rd, 424 const Register& rn, 425 const Register& rm, 426 Condition cond) 427 428 429 ### CSINV ### 430 431 Conditional select inversion: rd = cond ? rn : ~rm. 432 433 void csinv(const Register& rd, 434 const Register& rn, 435 const Register& rm, 436 Condition cond) 437 438 439 ### CSNEG ### 440 441 Conditional select negation: rd = cond ? rn : -rm. 442 443 void csneg(const Register& rd, 444 const Register& rn, 445 const Register& rm, 446 Condition cond) 447 448 449 ### DC ### 450 451 System data cache operation. 452 453 void dc(DataCacheOp op, const Register& rt) 454 455 456 ### DMB ### 457 458 Data memory barrier. 459 460 void dmb(BarrierDomain domain, BarrierType type) 461 462 463 ### DSB ### 464 465 Data synchronization barrier. 466 467 void dsb(BarrierDomain domain, BarrierType type) 468 469 470 ### EON ### 471 472 Bitwise enor/xnor (A ^ ~B). 473 474 void eon(const Register& rd, const Register& rn, const Operand& operand) 475 476 477 ### EOR ### 478 479 Bitwise eor/xor (A ^ B). 480 481 void eor(const Register& rd, const Register& rn, const Operand& operand) 482 483 484 ### EXTR ### 485 486 Extract. 487 488 void extr(const Register& rd, 489 const Register& rn, 490 const Register& rm, 491 unsigned lsb) 492 493 494 ### HINT ### 495 496 System hint. 497 498 void hint(SystemHint code) 499 500 501 ### HLT ### 502 503 Halting debug-mode breakpoint. 504 505 void hlt(int code) 506 507 508 ### IC ### 509 510 System instruction cache operation. 511 512 void ic(InstructionCacheOp op, const Register& rt) 513 514 515 ### ISB ### 516 517 Instruction synchronization barrier. 518 519 void isb() 520 521 522 ### LDAR ### 523 524 Load-acquire register. 525 526 void ldar(const Register& rt, const MemOperand& src) 527 528 529 ### LDARB ### 530 531 Load-acquire byte. 532 533 void ldarb(const Register& rt, const MemOperand& src) 534 535 536 ### LDARH ### 537 538 Load-acquire half-word. 539 540 void ldarh(const Register& rt, const MemOperand& src) 541 542 543 ### LDAXP ### 544 545 Load-acquire exclusive register pair. 546 547 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) 548 549 550 ### LDAXR ### 551 552 Load-acquire exclusive register. 553 554 void ldaxr(const Register& rt, const MemOperand& src) 555 556 557 ### LDAXRB ### 558 559 Load-acquire exclusive byte. 560 561 void ldaxrb(const Register& rt, const MemOperand& src) 562 563 564 ### LDAXRH ### 565 566 Load-acquire exclusive half-word. 567 568 void ldaxrh(const Register& rt, const MemOperand& src) 569 570 571 ### LDNP ### 572 573 Load integer or FP register pair, non-temporal. 574 575 void ldnp(const CPURegister& rt, const CPURegister& rt2, 576 const MemOperand& src) 577 578 579 ### LDP ### 580 581 Load integer or FP register pair. 582 583 void ldp(const CPURegister& rt, const CPURegister& rt2, 584 const MemOperand& src) 585 586 587 ### LDPSW ### 588 589 Load word pair with sign extension. 590 591 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src) 592 593 594 ### LDR ### 595 596 Load integer or FP register from literal pool. 597 598 void ldr(const CPURegister& rt, RawLiteral* literal) 599 600 601 ### LDR ### 602 603 Load integer or FP register from pc + imm19 << 2. 604 605 void ldr(const CPURegister& rt, int imm19) 606 607 608 ### LDR ### 609 610 Load integer or FP register. 611 612 void ldr(const CPURegister& rt, const MemOperand& src, 613 LoadStoreScalingOption option = PreferScaledOffset) 614 615 616 ### LDRB ### 617 618 Load byte. 619 620 void ldrb(const Register& rt, const MemOperand& src, 621 LoadStoreScalingOption option = PreferScaledOffset) 622 623 624 ### LDRH ### 625 626 Load half-word. 627 628 void ldrh(const Register& rt, const MemOperand& src, 629 LoadStoreScalingOption option = PreferScaledOffset) 630 631 632 ### LDRSB ### 633 634 Load byte with sign extension. 635 636 void ldrsb(const Register& rt, const MemOperand& src, 637 LoadStoreScalingOption option = PreferScaledOffset) 638 639 640 ### LDRSH ### 641 642 Load half-word with sign extension. 643 644 void ldrsh(const Register& rt, const MemOperand& src, 645 LoadStoreScalingOption option = PreferScaledOffset) 646 647 648 ### LDRSW ### 649 650 Load word with sign extension from literal pool. 651 652 void ldrsw(const Register& rt, RawLiteral* literal) 653 654 655 ### LDRSW ### 656 657 Load word with sign extension from pc + imm19 << 2. 658 659 void ldrsw(const Register& rt, int imm19) 660 661 662 ### LDRSW ### 663 664 Load word with sign extension. 665 666 void ldrsw(const Register& rt, const MemOperand& src, 667 LoadStoreScalingOption option = PreferScaledOffset) 668 669 670 ### LDUR ### 671 672 Load integer or FP register (with unscaled offset). 673 674 void ldur(const CPURegister& rt, const MemOperand& src, 675 LoadStoreScalingOption option = PreferUnscaledOffset) 676 677 678 ### LDURB ### 679 680 Load byte (with unscaled offset). 681 682 void ldurb(const Register& rt, const MemOperand& src, 683 LoadStoreScalingOption option = PreferUnscaledOffset) 684 685 686 ### LDURH ### 687 688 Load half-word (with unscaled offset). 689 690 void ldurh(const Register& rt, const MemOperand& src, 691 LoadStoreScalingOption option = PreferUnscaledOffset) 692 693 694 ### LDURSB ### 695 696 Load byte with sign extension (and unscaled offset). 697 698 void ldursb(const Register& rt, const MemOperand& src, 699 LoadStoreScalingOption option = PreferUnscaledOffset) 700 701 702 ### LDURSH ### 703 704 Load half-word with sign extension (and unscaled offset). 705 706 void ldursh(const Register& rt, const MemOperand& src, 707 LoadStoreScalingOption option = PreferUnscaledOffset) 708 709 710 ### LDURSW ### 711 712 Load word with sign extension. 713 714 void ldursw(const Register& rt, const MemOperand& src, 715 LoadStoreScalingOption option = PreferUnscaledOffset) 716 717 718 ### LDXP ### 719 720 Load exclusive register pair. 721 722 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src) 723 724 725 ### LDXR ### 726 727 Load exclusive register. 728 729 void ldxr(const Register& rt, const MemOperand& src) 730 731 732 ### LDXRB ### 733 734 Load exclusive byte. 735 736 void ldxrb(const Register& rt, const MemOperand& src) 737 738 739 ### LDXRH ### 740 741 Load exclusive half-word. 742 743 void ldxrh(const Register& rt, const MemOperand& src) 744 745 746 ### LSL ### 747 748 Logical shift left. 749 750 void lsl(const Register& rd, const Register& rn, unsigned shift) 751 752 753 ### LSLV ### 754 755 Logical shift left by variable. 756 757 void lslv(const Register& rd, const Register& rn, const Register& rm) 758 759 760 ### LSR ### 761 762 Logical shift right. 763 764 void lsr(const Register& rd, const Register& rn, unsigned shift) 765 766 767 ### LSRV ### 768 769 Logical shift right by variable. 770 771 void lsrv(const Register& rd, const Register& rn, const Register& rm) 772 773 774 ### MADD ### 775 776 Multiply and accumulate. 777 778 void madd(const Register& rd, 779 const Register& rn, 780 const Register& rm, 781 const Register& ra) 782 783 784 ### MNEG ### 785 786 Negated multiply. 787 788 void mneg(const Register& rd, const Register& rn, const Register& rm) 789 790 791 ### MOV ### 792 793 Move register to register. 794 795 void mov(const Register& rd, const Register& rn) 796 797 798 ### MOVK ### 799 800 Move immediate and keep. 801 802 void movk(const Register& rd, uint64_t imm, int shift = -1) 803 804 805 ### MOVN ### 806 807 Move inverted immediate. 808 809 void movn(const Register& rd, uint64_t imm, int shift = -1) 810 811 812 ### MOVZ ### 813 814 Move immediate. 815 816 void movz(const Register& rd, uint64_t imm, int shift = -1) 817 818 819 ### MRS ### 820 821 Move to register from system register. 822 823 void mrs(const Register& rt, SystemRegister sysreg) 824 825 826 ### MSR ### 827 828 Move from register to system register. 829 830 void msr(SystemRegister sysreg, const Register& rt) 831 832 833 ### MSUB ### 834 835 Multiply and subtract. 836 837 void msub(const Register& rd, 838 const Register& rn, 839 const Register& rm, 840 const Register& ra) 841 842 843 ### MUL ### 844 845 Multiply. 846 847 void mul(const Register& rd, const Register& rn, const Register& rm) 848 849 850 ### MVN ### 851 852 Move inverted operand to register. 853 854 void mvn(const Register& rd, const Operand& operand) 855 856 857 ### NEG ### 858 859 Negate. 860 861 void neg(const Register& rd, 862 const Operand& operand) 863 864 865 ### NEGS ### 866 867 Negate and update status flags. 868 869 void negs(const Register& rd, 870 const Operand& operand) 871 872 873 ### NGC ### 874 875 Negate with carry bit. 876 877 void ngc(const Register& rd, 878 const Operand& operand) 879 880 881 ### NGCS ### 882 883 Negate with carry bit and update status flags. 884 885 void ngcs(const Register& rd, 886 const Operand& operand) 887 888 889 ### NOP ### 890 891 No-op. 892 893 void nop() 894 895 896 ### ORN ### 897 898 Bitwise nor (A | ~B). 899 900 void orn(const Register& rd, const Register& rn, const Operand& operand) 901 902 903 ### ORR ### 904 905 Bitwise or (A | B). 906 907 void orr(const Register& rd, const Register& rn, const Operand& operand) 908 909 910 ### PRFM ### 911 912 Prefetch from pc + imm19 << 2. 913 914 void prfm(PrefetchOperation op, int imm19) 915 916 917 ### PRFM ### 918 919 Prefetch memory in the literal pool. 920 921 void prfm(PrefetchOperation op, RawLiteral* literal) 922 923 924 ### PRFM ### 925 926 Prefetch memory. 927 928 void prfm(PrefetchOperation op, const MemOperand& addr, 929 LoadStoreScalingOption option = PreferScaledOffset) 930 931 932 ### PRFUM ### 933 934 Prefetch memory (with unscaled offset). 935 936 void prfum(PrefetchOperation op, const MemOperand& addr, 937 LoadStoreScalingOption option = PreferUnscaledOffset) 938 939 940 ### RBIT ### 941 942 Bit reverse. 943 944 void rbit(const Register& rd, const Register& rn) 945 946 947 ### RET ### 948 949 Branch to register with return hint. 950 951 void ret(const Register& xn = lr) 952 953 954 ### REV ### 955 956 Reverse bytes. 957 958 void rev(const Register& rd, const Register& rn) 959 960 961 ### REV16 ### 962 963 Reverse bytes in 16-bit half words. 964 965 void rev16(const Register& rd, const Register& rn) 966 967 968 ### REV32 ### 969 970 Reverse bytes in 32-bit words. 971 972 void rev32(const Register& rd, const Register& rn) 973 974 975 ### ROR ### 976 977 Rotate right. 978 979 void ror(const Register& rd, const Register& rs, unsigned shift) 980 981 982 ### RORV ### 983 984 Rotate right by variable. 985 986 void rorv(const Register& rd, const Register& rn, const Register& rm) 987 988 989 ### SBC ### 990 991 Subtract with carry bit. 992 993 void sbc(const Register& rd, 994 const Register& rn, 995 const Operand& operand) 996 997 998 ### SBCS ### 999 1000 Subtract with carry bit and update status flags. 1001 1002 void sbcs(const Register& rd, 1003 const Register& rn, 1004 const Operand& operand) 1005 1006 1007 ### SBFIZ ### 1008 1009 Signed bitfield insert with zero at right. 1010 1011 void sbfiz(const Register& rd, 1012 const Register& rn, 1013 unsigned lsb, 1014 unsigned width) 1015 1016 1017 ### SBFM ### 1018 1019 Signed bitfield move. 1020 1021 void sbfm(const Register& rd, 1022 const Register& rn, 1023 unsigned immr, 1024 unsigned imms) 1025 1026 1027 ### SBFX ### 1028 1029 Signed bitfield extract. 1030 1031 void sbfx(const Register& rd, 1032 const Register& rn, 1033 unsigned lsb, 1034 unsigned width) 1035 1036 1037 ### SDIV ### 1038 1039 Signed integer divide. 1040 1041 void sdiv(const Register& rd, const Register& rn, const Register& rm) 1042 1043 1044 ### SMADDL ### 1045 1046 Signed long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1047 1048 void smaddl(const Register& rd, 1049 const Register& rn, 1050 const Register& rm, 1051 const Register& ra) 1052 1053 1054 ### SMSUBL ### 1055 1056 Signed long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1057 1058 void smsubl(const Register& rd, 1059 const Register& rn, 1060 const Register& rm, 1061 const Register& ra) 1062 1063 1064 ### SMULH ### 1065 1066 Signed multiply high: 64 x 64 -> 64-bit <127:64>. 1067 1068 void smulh(const Register& xd, const Register& xn, const Register& xm) 1069 1070 1071 ### SMULL ### 1072 1073 Signed long multiply: 32 x 32 -> 64-bit. 1074 1075 void smull(const Register& rd, const Register& rn, const Register& rm) 1076 1077 1078 ### STLR ### 1079 1080 Store-release register. 1081 1082 void stlr(const Register& rt, const MemOperand& dst) 1083 1084 1085 ### STLRB ### 1086 1087 Store-release byte. 1088 1089 void stlrb(const Register& rt, const MemOperand& dst) 1090 1091 1092 ### STLRH ### 1093 1094 Store-release half-word. 1095 1096 void stlrh(const Register& rt, const MemOperand& dst) 1097 1098 1099 ### STLXP ### 1100 1101 Store-release exclusive register pair. 1102 1103 void stlxp(const Register& rs, 1104 const Register& rt, 1105 const Register& rt2, 1106 const MemOperand& dst) 1107 1108 1109 ### STLXR ### 1110 1111 Store-release exclusive register. 1112 1113 void stlxr(const Register& rs, const Register& rt, const MemOperand& dst) 1114 1115 1116 ### STLXRB ### 1117 1118 Store-release exclusive byte. 1119 1120 void stlxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1121 1122 1123 ### STLXRH ### 1124 1125 Store-release exclusive half-word. 1126 1127 void stlxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1128 1129 1130 ### STNP ### 1131 1132 Store integer or FP register pair, non-temporal. 1133 1134 void stnp(const CPURegister& rt, const CPURegister& rt2, 1135 const MemOperand& dst) 1136 1137 1138 ### STP ### 1139 1140 Store integer or FP register pair. 1141 1142 void stp(const CPURegister& rt, const CPURegister& rt2, 1143 const MemOperand& dst) 1144 1145 1146 ### STR ### 1147 1148 Store integer or FP register. 1149 1150 void str(const CPURegister& rt, const MemOperand& dst, 1151 LoadStoreScalingOption option = PreferScaledOffset) 1152 1153 1154 ### STRB ### 1155 1156 Store byte. 1157 1158 void strb(const Register& rt, const MemOperand& dst, 1159 LoadStoreScalingOption option = PreferScaledOffset) 1160 1161 1162 ### STRH ### 1163 1164 Store half-word. 1165 1166 void strh(const Register& rt, const MemOperand& dst, 1167 LoadStoreScalingOption option = PreferScaledOffset) 1168 1169 1170 ### STUR ### 1171 1172 Store integer or FP register (with unscaled offset). 1173 1174 void stur(const CPURegister& rt, const MemOperand& src, 1175 LoadStoreScalingOption option = PreferUnscaledOffset) 1176 1177 1178 ### STURB ### 1179 1180 Store byte (with unscaled offset). 1181 1182 void sturb(const Register& rt, const MemOperand& dst, 1183 LoadStoreScalingOption option = PreferUnscaledOffset) 1184 1185 1186 ### STURH ### 1187 1188 Store half-word (with unscaled offset). 1189 1190 void sturh(const Register& rt, const MemOperand& dst, 1191 LoadStoreScalingOption option = PreferUnscaledOffset) 1192 1193 1194 ### STXP ### 1195 1196 Store exclusive register pair. 1197 1198 void stxp(const Register& rs, 1199 const Register& rt, 1200 const Register& rt2, 1201 const MemOperand& dst) 1202 1203 1204 ### STXR ### 1205 1206 Store exclusive register. 1207 1208 void stxr(const Register& rs, const Register& rt, const MemOperand& dst) 1209 1210 1211 ### STXRB ### 1212 1213 Store exclusive byte. 1214 1215 void stxrb(const Register& rs, const Register& rt, const MemOperand& dst) 1216 1217 1218 ### STXRH ### 1219 1220 Store exclusive half-word. 1221 1222 void stxrh(const Register& rs, const Register& rt, const MemOperand& dst) 1223 1224 1225 ### SUB ### 1226 1227 Subtract. 1228 1229 void sub(const Register& rd, 1230 const Register& rn, 1231 const Operand& operand) 1232 1233 1234 ### SUBS ### 1235 1236 Subtract and update status flags. 1237 1238 void subs(const Register& rd, 1239 const Register& rn, 1240 const Operand& operand) 1241 1242 1243 ### SVC ### 1244 1245 Generate exception targeting EL1. 1246 1247 void svc(int code) 1248 1249 1250 ### SXTB ### 1251 1252 Signed extend byte. 1253 1254 void sxtb(const Register& rd, const Register& rn) 1255 1256 1257 ### SXTH ### 1258 1259 Signed extend halfword. 1260 1261 void sxth(const Register& rd, const Register& rn) 1262 1263 1264 ### SXTW ### 1265 1266 Signed extend word. 1267 1268 void sxtw(const Register& rd, const Register& rn) 1269 1270 1271 ### SYS ### 1272 1273 System instruction with pre-encoded op (op1:crn:crm:op2). 1274 1275 void sys(int op, const Register& rt = xzr) 1276 1277 1278 ### SYS ### 1279 1280 System instruction. 1281 1282 void sys(int op1, int crn, int crm, int op2, const Register& rt = xzr) 1283 1284 1285 ### TBNZ ### 1286 1287 Test bit and branch to PC offset if not zero. 1288 1289 void tbnz(const Register& rt, unsigned bit_pos, int imm14) 1290 1291 1292 ### TBNZ ### 1293 1294 Test bit and branch to label if not zero. 1295 1296 void tbnz(const Register& rt, unsigned bit_pos, Label* label) 1297 1298 1299 ### TBZ ### 1300 1301 Test bit and branch to PC offset if zero. 1302 1303 void tbz(const Register& rt, unsigned bit_pos, int imm14) 1304 1305 1306 ### TBZ ### 1307 1308 Test bit and branch to label if zero. 1309 1310 void tbz(const Register& rt, unsigned bit_pos, Label* label) 1311 1312 1313 ### TST ### 1314 1315 Bit test and set flags. 1316 1317 void tst(const Register& rn, const Operand& operand) 1318 1319 1320 ### UBFIZ ### 1321 1322 Unsigned bitfield insert with zero at right. 1323 1324 void ubfiz(const Register& rd, 1325 const Register& rn, 1326 unsigned lsb, 1327 unsigned width) 1328 1329 1330 ### UBFM ### 1331 1332 Unsigned bitfield move. 1333 1334 void ubfm(const Register& rd, 1335 const Register& rn, 1336 unsigned immr, 1337 unsigned imms) 1338 1339 1340 ### UBFX ### 1341 1342 Unsigned bitfield extract. 1343 1344 void ubfx(const Register& rd, 1345 const Register& rn, 1346 unsigned lsb, 1347 unsigned width) 1348 1349 1350 ### UDIV ### 1351 1352 Unsigned integer divide. 1353 1354 void udiv(const Register& rd, const Register& rn, const Register& rm) 1355 1356 1357 ### UMADDL ### 1358 1359 Unsigned long multiply and accumulate: 32 x 32 + 64 -> 64-bit. 1360 1361 void umaddl(const Register& rd, 1362 const Register& rn, 1363 const Register& rm, 1364 const Register& ra) 1365 1366 1367 ### UMSUBL ### 1368 1369 Unsigned long multiply and subtract: 64 - (32 x 32) -> 64-bit. 1370 1371 void umsubl(const Register& rd, 1372 const Register& rn, 1373 const Register& rm, 1374 const Register& ra) 1375 1376 1377 ### UXTB ### 1378 1379 Unsigned extend byte. 1380 1381 void uxtb(const Register& rd, const Register& rn) 1382 1383 1384 ### UXTH ### 1385 1386 Unsigned extend halfword. 1387 1388 void uxth(const Register& rd, const Register& rn) 1389 1390 1391 ### UXTW ### 1392 1393 Unsigned extend word. 1394 1395 void uxtw(const Register& rd, const Register& rn) 1396 1397 1398 1399 AArch64 floating point and NEON instructions 1400 -------------------------------------------- 1401 1402 ### ABS ### 1403 1404 Absolute value. 1405 1406 void abs(const VRegister& vd, 1407 const VRegister& vn) 1408 1409 1410 ### ADD ### 1411 1412 Add. 1413 1414 void add(const VRegister& vd, 1415 const VRegister& vn, 1416 const VRegister& vm) 1417 1418 1419 ### ADDHN ### 1420 1421 Add narrow returning high half. 1422 1423 void addhn(const VRegister& vd, 1424 const VRegister& vn, 1425 const VRegister& vm) 1426 1427 1428 ### ADDHN2 ### 1429 1430 Add narrow returning high half (second part). 1431 1432 void addhn2(const VRegister& vd, 1433 const VRegister& vn, 1434 const VRegister& vm) 1435 1436 1437 ### ADDP ### 1438 1439 Add pair of elements scalar. 1440 1441 void addp(const VRegister& vd, 1442 const VRegister& vn) 1443 1444 1445 ### ADDP ### 1446 1447 Add pairwise. 1448 1449 void addp(const VRegister& vd, 1450 const VRegister& vn, 1451 const VRegister& vm) 1452 1453 1454 ### ADDV ### 1455 1456 Add across vector. 1457 1458 void addv(const VRegister& vd, 1459 const VRegister& vn) 1460 1461 1462 ### AND ### 1463 1464 Bitwise and. 1465 1466 void and_(const VRegister& vd, 1467 const VRegister& vn, 1468 const VRegister& vm) 1469 1470 1471 ### BIC ### 1472 1473 Bit clear immediate. 1474 1475 void bic(const VRegister& vd, 1476 const int imm8, 1477 const int left_shift = 0) 1478 1479 1480 ### BIC ### 1481 1482 Bit clear. 1483 1484 void bic(const VRegister& vd, 1485 const VRegister& vn, 1486 const VRegister& vm) 1487 1488 1489 ### BIF ### 1490 1491 Bitwise insert if false. 1492 1493 void bif(const VRegister& vd, 1494 const VRegister& vn, 1495 const VRegister& vm) 1496 1497 1498 ### BIT ### 1499 1500 Bitwise insert if true. 1501 1502 void bit(const VRegister& vd, 1503 const VRegister& vn, 1504 const VRegister& vm) 1505 1506 1507 ### BSL ### 1508 1509 Bitwise select. 1510 1511 void bsl(const VRegister& vd, 1512 const VRegister& vn, 1513 const VRegister& vm) 1514 1515 1516 ### CLS ### 1517 1518 Count leading sign bits. 1519 1520 void cls(const VRegister& vd, 1521 const VRegister& vn) 1522 1523 1524 ### CLZ ### 1525 1526 Count leading zero bits (vector). 1527 1528 void clz(const VRegister& vd, 1529 const VRegister& vn) 1530 1531 1532 ### CMEQ ### 1533 1534 Compare bitwise to zero. 1535 1536 void cmeq(const VRegister& vd, 1537 const VRegister& vn, 1538 int value) 1539 1540 1541 ### CMEQ ### 1542 1543 Compare equal. 1544 1545 void cmeq(const VRegister& vd, 1546 const VRegister& vn, 1547 const VRegister& vm) 1548 1549 1550 ### CMGE ### 1551 1552 Compare signed greater than or equal to zero. 1553 1554 void cmge(const VRegister& vd, 1555 const VRegister& vn, 1556 int value) 1557 1558 1559 ### CMGE ### 1560 1561 Compare signed greater than or equal. 1562 1563 void cmge(const VRegister& vd, 1564 const VRegister& vn, 1565 const VRegister& vm) 1566 1567 1568 ### CMGT ### 1569 1570 Compare signed greater than zero. 1571 1572 void cmgt(const VRegister& vd, 1573 const VRegister& vn, 1574 int value) 1575 1576 1577 ### CMGT ### 1578 1579 Compare signed greater than. 1580 1581 void cmgt(const VRegister& vd, 1582 const VRegister& vn, 1583 const VRegister& vm) 1584 1585 1586 ### CMHI ### 1587 1588 Compare unsigned higher. 1589 1590 void cmhi(const VRegister& vd, 1591 const VRegister& vn, 1592 const VRegister& vm) 1593 1594 1595 ### CMHS ### 1596 1597 Compare unsigned higher or same. 1598 1599 void cmhs(const VRegister& vd, 1600 const VRegister& vn, 1601 const VRegister& vm) 1602 1603 1604 ### CMLE ### 1605 1606 Compare signed less than or equal to zero. 1607 1608 void cmle(const VRegister& vd, 1609 const VRegister& vn, 1610 int value) 1611 1612 1613 ### CMLT ### 1614 1615 Compare signed less than zero. 1616 1617 void cmlt(const VRegister& vd, 1618 const VRegister& vn, 1619 int value) 1620 1621 1622 ### CMTST ### 1623 1624 Compare bitwise test bits nonzero. 1625 1626 void cmtst(const VRegister& vd, 1627 const VRegister& vn, 1628 const VRegister& vm) 1629 1630 1631 ### CNT ### 1632 1633 Population count per byte. 1634 1635 void cnt(const VRegister& vd, 1636 const VRegister& vn) 1637 1638 1639 ### DUP ### 1640 1641 Duplicate general-purpose register to vector. 1642 1643 void dup(const VRegister& vd, 1644 const Register& rn) 1645 1646 1647 ### DUP ### 1648 1649 Duplicate vector element to vector or scalar. 1650 1651 void dup(const VRegister& vd, 1652 const VRegister& vn, 1653 int vn_index) 1654 1655 1656 ### EOR ### 1657 1658 Bitwise eor. 1659 1660 void eor(const VRegister& vd, 1661 const VRegister& vn, 1662 const VRegister& vm) 1663 1664 1665 ### EXT ### 1666 1667 Extract vector from pair of vectors. 1668 1669 void ext(const VRegister& vd, 1670 const VRegister& vn, 1671 const VRegister& vm, 1672 int index) 1673 1674 1675 ### FABD ### 1676 1677 FP absolute difference. 1678 1679 void fabd(const VRegister& vd, 1680 const VRegister& vn, 1681 const VRegister& vm) 1682 1683 1684 ### FABS ### 1685 1686 FP absolute. 1687 1688 void fabs(const VRegister& vd, const VRegister& vn) 1689 1690 1691 ### FACGE ### 1692 1693 FP absolute greater than or equal. 1694 1695 void facge(const VRegister& vd, 1696 const VRegister& vn, 1697 const VRegister& vm) 1698 1699 1700 ### FACGT ### 1701 1702 FP absolute greater than. 1703 1704 void facgt(const VRegister& vd, 1705 const VRegister& vn, 1706 const VRegister& vm) 1707 1708 1709 ### FADD ### 1710 1711 FP add. 1712 1713 void fadd(const VRegister& vd, const VRegister& vn, const VRegister& vm) 1714 1715 1716 ### FADDP ### 1717 1718 FP pairwise add scalar. 1719 1720 void faddp(const VRegister& vd, 1721 const VRegister& vn) 1722 1723 1724 ### FADDP ### 1725 1726 FP pairwise add vector. 1727 1728 void faddp(const VRegister& vd, 1729 const VRegister& vn, 1730 const VRegister& vm) 1731 1732 1733 ### FCCMP ### 1734 1735 FP conditional compare. 1736 1737 void fccmp(const VRegister& vn, 1738 const VRegister& vm, 1739 StatusFlags nzcv, 1740 Condition cond) 1741 1742 1743 ### FCMEQ ### 1744 1745 FP compare equal to zero. 1746 1747 void fcmeq(const VRegister& vd, 1748 const VRegister& vn, 1749 double imm) 1750 1751 1752 ### FCMEQ ### 1753 1754 FP compare equal. 1755 1756 void fcmeq(const VRegister& vd, 1757 const VRegister& vn, 1758 const VRegister& vm) 1759 1760 1761 ### FCMGE ### 1762 1763 FP greater than or equal to zero. 1764 1765 void fcmge(const VRegister& vd, 1766 const VRegister& vn, 1767 double imm) 1768 1769 1770 ### FCMGE ### 1771 1772 FP greater than or equal. 1773 1774 void fcmge(const VRegister& vd, 1775 const VRegister& vn, 1776 const VRegister& vm) 1777 1778 1779 ### FCMGT ### 1780 1781 FP greater than zero. 1782 1783 void fcmgt(const VRegister& vd, 1784 const VRegister& vn, 1785 double imm) 1786 1787 1788 ### FCMGT ### 1789 1790 FP greater than. 1791 1792 void fcmgt(const VRegister& vd, 1793 const VRegister& vn, 1794 const VRegister& vm) 1795 1796 1797 ### FCMLE ### 1798 1799 FP less than or equal to zero. 1800 1801 void fcmle(const VRegister& vd, 1802 const VRegister& vn, 1803 double imm) 1804 1805 1806 ### FCMLT ### 1807 1808 FP less than to zero. 1809 1810 void fcmlt(const VRegister& vd, 1811 const VRegister& vn, 1812 double imm) 1813 1814 1815 ### FCMP ### 1816 1817 FP compare immediate. 1818 1819 void fcmp(const VRegister& vn, double value) 1820 1821 1822 ### FCMP ### 1823 1824 FP compare registers. 1825 1826 void fcmp(const VRegister& vn, const VRegister& vm) 1827 1828 1829 ### FCSEL ### 1830 1831 FP conditional select. 1832 1833 void fcsel(const VRegister& vd, 1834 const VRegister& vn, 1835 const VRegister& vm, 1836 Condition cond) 1837 1838 1839 ### FCVT ### 1840 1841 FP convert between precisions. 1842 1843 void fcvt(const VRegister& vd, const VRegister& vn) 1844 1845 1846 ### FCVTAS ### 1847 1848 FP convert to signed integer, nearest with ties to away. 1849 1850 void fcvtas(const Register& rd, const VRegister& vn) 1851 1852 1853 ### FCVTAS ### 1854 1855 FP convert to signed integer, nearest with ties to away. 1856 1857 void fcvtas(const VRegister& vd, const VRegister& vn) 1858 1859 1860 ### FCVTAU ### 1861 1862 FP convert to unsigned integer, nearest with ties to away. 1863 1864 void fcvtau(const Register& rd, const VRegister& vn) 1865 1866 1867 ### FCVTAU ### 1868 1869 FP convert to unsigned integer, nearest with ties to away. 1870 1871 void fcvtau(const VRegister& vd, const VRegister& vn) 1872 1873 1874 ### FCVTL ### 1875 1876 FP convert to higher precision. 1877 1878 void fcvtl(const VRegister& vd, const VRegister& vn) 1879 1880 1881 ### FCVTL2 ### 1882 1883 FP convert to higher precision (second part). 1884 1885 void fcvtl2(const VRegister& vd, const VRegister& vn) 1886 1887 1888 ### FCVTMS ### 1889 1890 FP convert to signed integer, round towards -infinity. 1891 1892 void fcvtms(const VRegister& vd, const VRegister& vn) 1893 1894 1895 ### FCVTMS ### 1896 1897 FP convert to signed integer, round towards -infinity. 1898 1899 void fcvtms(const Register& rd, const VRegister& vn) 1900 1901 1902 ### FCVTMU ### 1903 1904 FP convert to unsigned integer, round towards -infinity. 1905 1906 void fcvtmu(const VRegister& vd, const VRegister& vn) 1907 1908 1909 ### FCVTMU ### 1910 1911 FP convert to unsigned integer, round towards -infinity. 1912 1913 void fcvtmu(const Register& rd, const VRegister& vn) 1914 1915 1916 ### FCVTN ### 1917 1918 FP convert to lower precision. 1919 1920 void fcvtn(const VRegister& vd, const VRegister& vn) 1921 1922 1923 ### FCVTN2 ### 1924 1925 FP convert to lower prevision (second part). 1926 1927 void fcvtn2(const VRegister& vd, const VRegister& vn) 1928 1929 1930 ### FCVTNS ### 1931 1932 FP convert to signed integer, nearest with ties to even. 1933 1934 void fcvtns(const Register& rd, const VRegister& vn) 1935 1936 1937 ### FCVTNS ### 1938 1939 FP convert to signed integer, nearest with ties to even. 1940 1941 void fcvtns(const VRegister& rd, const VRegister& vn) 1942 1943 1944 ### FCVTNU ### 1945 1946 FP convert to unsigned integer, nearest with ties to even. 1947 1948 void fcvtnu(const Register& rd, const VRegister& vn) 1949 1950 1951 ### FCVTNU ### 1952 1953 FP convert to unsigned integer, nearest with ties to even. 1954 1955 void fcvtnu(const VRegister& rd, const VRegister& vn) 1956 1957 1958 ### FCVTPS ### 1959 1960 FP convert to signed integer, round towards +infinity. 1961 1962 void fcvtps(const VRegister& vd, const VRegister& vn) 1963 1964 1965 ### FCVTPS ### 1966 1967 FP convert to signed integer, round towards +infinity. 1968 1969 void fcvtps(const Register& rd, const VRegister& vn) 1970 1971 1972 ### FCVTPU ### 1973 1974 FP convert to unsigned integer, round towards +infinity. 1975 1976 void fcvtpu(const VRegister& vd, const VRegister& vn) 1977 1978 1979 ### FCVTPU ### 1980 1981 FP convert to unsigned integer, round towards +infinity. 1982 1983 void fcvtpu(const Register& rd, const VRegister& vn) 1984 1985 1986 ### FCVTXN ### 1987 1988 FP convert to lower precision, rounding to odd. 1989 1990 void fcvtxn(const VRegister& vd, const VRegister& vn) 1991 1992 1993 ### FCVTXN2 ### 1994 1995 FP convert to lower precision, rounding to odd (second part). 1996 1997 void fcvtxn2(const VRegister& vd, const VRegister& vn) 1998 1999 2000 ### FCVTZS ### 2001 2002 FP convert to signed integer or fixed-point, round towards zero. 2003 2004 void fcvtzs(const VRegister& vd, const VRegister& vn, int fbits = 0) 2005 2006 2007 ### FCVTZS ### 2008 2009 FP convert to signed integer or fixed-point, round towards zero. 2010 2011 void fcvtzs(const Register& rd, const VRegister& vn, int fbits = 0) 2012 2013 2014 ### FCVTZU ### 2015 2016 FP convert to unsigned integer or fixed-point, round towards zero. 2017 2018 void fcvtzu(const Register& rd, const VRegister& vn, int fbits = 0) 2019 2020 2021 ### FCVTZU ### 2022 2023 FP convert to unsigned integer or fixed-point, round towards zero. 2024 2025 void fcvtzu(const VRegister& vd, const VRegister& vn, int fbits = 0) 2026 2027 2028 ### FDIV ### 2029 2030 FP divide. 2031 2032 void fdiv(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2033 2034 2035 ### FMADD ### 2036 2037 FP fused multiply-add. 2038 2039 void fmadd(const VRegister& vd, 2040 const VRegister& vn, 2041 const VRegister& vm, 2042 const VRegister& va) 2043 2044 2045 ### FMAX ### 2046 2047 FP maximum. 2048 2049 void fmax(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2050 2051 2052 ### FMAXNM ### 2053 2054 FP maximum number. 2055 2056 void fmaxnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2057 2058 2059 ### FMAXNMP ### 2060 2061 FP pairwise maximum number scalar. 2062 2063 void fmaxnmp(const VRegister& vd, 2064 const VRegister& vn) 2065 2066 2067 ### FMAXNMP ### 2068 2069 FP pairwise maximum number vector. 2070 2071 void fmaxnmp(const VRegister& vd, 2072 const VRegister& vn, 2073 const VRegister& vm) 2074 2075 2076 ### FMAXNMV ### 2077 2078 FP maximum number across vector. 2079 2080 void fmaxnmv(const VRegister& vd, 2081 const VRegister& vn) 2082 2083 2084 ### FMAXP ### 2085 2086 FP pairwise maximum scalar. 2087 2088 void fmaxp(const VRegister& vd, 2089 const VRegister& vn) 2090 2091 2092 ### FMAXP ### 2093 2094 FP pairwise maximum vector. 2095 2096 void fmaxp(const VRegister& vd, 2097 const VRegister& vn, 2098 const VRegister& vm) 2099 2100 2101 ### FMAXV ### 2102 2103 FP maximum across vector. 2104 2105 void fmaxv(const VRegister& vd, 2106 const VRegister& vn) 2107 2108 2109 ### FMIN ### 2110 2111 FP minimum. 2112 2113 void fmin(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2114 2115 2116 ### FMINNM ### 2117 2118 FP minimum number. 2119 2120 void fminnm(const VRegister& vd, const VRegister& fn, const VRegister& vm) 2121 2122 2123 ### FMINNMP ### 2124 2125 FP pairwise minimum number scalar. 2126 2127 void fminnmp(const VRegister& vd, 2128 const VRegister& vn) 2129 2130 2131 ### FMINNMP ### 2132 2133 FP pairwise minimum number vector. 2134 2135 void fminnmp(const VRegister& vd, 2136 const VRegister& vn, 2137 const VRegister& vm) 2138 2139 2140 ### FMINNMV ### 2141 2142 FP minimum number across vector. 2143 2144 void fminnmv(const VRegister& vd, 2145 const VRegister& vn) 2146 2147 2148 ### FMINP ### 2149 2150 FP pairwise minimum scalar. 2151 2152 void fminp(const VRegister& vd, 2153 const VRegister& vn) 2154 2155 2156 ### FMINP ### 2157 2158 FP pairwise minimum vector. 2159 2160 void fminp(const VRegister& vd, 2161 const VRegister& vn, 2162 const VRegister& vm) 2163 2164 2165 ### FMINV ### 2166 2167 FP minimum across vector. 2168 2169 void fminv(const VRegister& vd, 2170 const VRegister& vn) 2171 2172 2173 ### FMLA ### 2174 2175 FP fused multiply-add to accumulator by element. 2176 2177 void fmla(const VRegister& vd, 2178 const VRegister& vn, 2179 const VRegister& vm, 2180 int vm_index) 2181 2182 2183 ### FMLA ### 2184 2185 FP vector multiply accumulate. 2186 2187 void fmla(const VRegister& vd, 2188 const VRegister& vn, 2189 const VRegister& vm) 2190 2191 2192 ### FMLS ### 2193 2194 FP fused multiply-sub from accumulator by element. 2195 2196 void fmls(const VRegister& vd, 2197 const VRegister& vn, 2198 const VRegister& vm, 2199 int vm_index) 2200 2201 2202 ### FMLS ### 2203 2204 FP vector multiply subtract. 2205 2206 void fmls(const VRegister& vd, 2207 const VRegister& vn, 2208 const VRegister& vm) 2209 2210 2211 ### FMOV ### 2212 2213 Move 64-bit register to top half of 128-bit FP register. 2214 2215 void fmov(const VRegister& vd, int index, const Register& rn) 2216 2217 2218 ### FMOV ### 2219 2220 Move FP register to FP register. 2221 2222 void fmov(const VRegister& vd, const VRegister& fn) 2223 2224 2225 ### FMOV ### 2226 2227 Move FP register to register. 2228 2229 void fmov(const Register& rd, const VRegister& fn) 2230 2231 2232 ### FMOV ### 2233 2234 Move double precision immediate to FP register. 2235 2236 void fmov(const VRegister& vd, double imm) 2237 2238 2239 ### FMOV ### 2240 2241 Move register to FP register. 2242 2243 void fmov(const VRegister& vd, const Register& rn) 2244 2245 2246 ### FMOV ### 2247 2248 Move single precision immediate to FP register. 2249 2250 void fmov(const VRegister& vd, float imm) 2251 2252 2253 ### FMOV ### 2254 2255 Move top half of 128-bit FP register to 64-bit register. 2256 2257 void fmov(const Register& rd, const VRegister& vn, int index) 2258 2259 2260 ### FMSUB ### 2261 2262 FP fused multiply-subtract. 2263 2264 void fmsub(const VRegister& vd, 2265 const VRegister& vn, 2266 const VRegister& vm, 2267 const VRegister& va) 2268 2269 2270 ### FMUL ### 2271 2272 FP multiply by element. 2273 2274 void fmul(const VRegister& vd, 2275 const VRegister& vn, 2276 const VRegister& vm, 2277 int vm_index) 2278 2279 2280 ### FMUL ### 2281 2282 FP multiply. 2283 2284 void fmul(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2285 2286 2287 ### FMULX ### 2288 2289 FP multiply extended by element. 2290 2291 void fmulx(const VRegister& vd, 2292 const VRegister& vn, 2293 const VRegister& vm, 2294 int vm_index) 2295 2296 2297 ### FMULX ### 2298 2299 FP vector multiply extended. 2300 2301 void fmulx(const VRegister& vd, 2302 const VRegister& vn, 2303 const VRegister& vm) 2304 2305 2306 ### FNEG ### 2307 2308 FP negate. 2309 2310 void fneg(const VRegister& vd, const VRegister& vn) 2311 2312 2313 ### FNMADD ### 2314 2315 FP fused multiply-add and negate. 2316 2317 void fnmadd(const VRegister& vd, 2318 const VRegister& vn, 2319 const VRegister& vm, 2320 const VRegister& va) 2321 2322 2323 ### FNMSUB ### 2324 2325 FP fused multiply-subtract and negate. 2326 2327 void fnmsub(const VRegister& vd, 2328 const VRegister& vn, 2329 const VRegister& vm, 2330 const VRegister& va) 2331 2332 2333 ### FNMUL ### 2334 2335 FP multiply-negate scalar. 2336 2337 void fnmul(const VRegister& vd, 2338 const VRegister& vn, 2339 const VRegister& vm) 2340 2341 2342 ### FRECPE ### 2343 2344 FP reciprocal estimate. 2345 2346 void frecpe(const VRegister& vd, 2347 const VRegister& vn) 2348 2349 2350 ### FRECPS ### 2351 2352 FP reciprocal step. 2353 2354 void frecps(const VRegister& vd, 2355 const VRegister& vn, 2356 const VRegister& vm) 2357 2358 2359 ### FRECPX ### 2360 2361 FP reciprocal exponent scalar. 2362 2363 void frecpx(const VRegister& vd, 2364 const VRegister& vn) 2365 2366 2367 ### FRINTA ### 2368 2369 FP round to integer, nearest with ties to away. 2370 2371 void frinta(const VRegister& vd, const VRegister& vn) 2372 2373 2374 ### FRINTI ### 2375 2376 FP round to integer, implicit rounding. 2377 2378 void frinti(const VRegister& vd, const VRegister& vn) 2379 2380 2381 ### FRINTM ### 2382 2383 FP round to integer, toward minus infinity. 2384 2385 void frintm(const VRegister& vd, const VRegister& vn) 2386 2387 2388 ### FRINTN ### 2389 2390 FP round to integer, nearest with ties to even. 2391 2392 void frintn(const VRegister& vd, const VRegister& vn) 2393 2394 2395 ### FRINTP ### 2396 2397 FP round to integer, toward plus infinity. 2398 2399 void frintp(const VRegister& vd, const VRegister& vn) 2400 2401 2402 ### FRINTX ### 2403 2404 FP round to integer, exact, implicit rounding. 2405 2406 void frintx(const VRegister& vd, const VRegister& vn) 2407 2408 2409 ### FRINTZ ### 2410 2411 FP round to integer, towards zero. 2412 2413 void frintz(const VRegister& vd, const VRegister& vn) 2414 2415 2416 ### FRSQRTE ### 2417 2418 FP reciprocal square root estimate. 2419 2420 void frsqrte(const VRegister& vd, 2421 const VRegister& vn) 2422 2423 2424 ### FRSQRTS ### 2425 2426 FP reciprocal square root step. 2427 2428 void frsqrts(const VRegister& vd, 2429 const VRegister& vn, 2430 const VRegister& vm) 2431 2432 2433 ### FSQRT ### 2434 2435 FP square root. 2436 2437 void fsqrt(const VRegister& vd, const VRegister& vn) 2438 2439 2440 ### FSUB ### 2441 2442 FP subtract. 2443 2444 void fsub(const VRegister& vd, const VRegister& vn, const VRegister& vm) 2445 2446 2447 ### INS ### 2448 2449 Insert vector element from another vector element. 2450 2451 void ins(const VRegister& vd, 2452 int vd_index, 2453 const VRegister& vn, 2454 int vn_index) 2455 2456 2457 ### INS ### 2458 2459 Insert vector element from general-purpose register. 2460 2461 void ins(const VRegister& vd, 2462 int vd_index, 2463 const Register& rn) 2464 2465 2466 ### LD1 ### 2467 2468 One-element single structure load to one lane. 2469 2470 void ld1(const VRegister& vt, 2471 int lane, 2472 const MemOperand& src) 2473 2474 2475 ### LD1 ### 2476 2477 One-element structure load to four registers. 2478 2479 void ld1(const VRegister& vt, 2480 const VRegister& vt2, 2481 const VRegister& vt3, 2482 const VRegister& vt4, 2483 const MemOperand& src) 2484 2485 2486 ### LD1 ### 2487 2488 One-element structure load to one register. 2489 2490 void ld1(const VRegister& vt, 2491 const MemOperand& src) 2492 2493 2494 ### LD1 ### 2495 2496 One-element structure load to three registers. 2497 2498 void ld1(const VRegister& vt, 2499 const VRegister& vt2, 2500 const VRegister& vt3, 2501 const MemOperand& src) 2502 2503 2504 ### LD1 ### 2505 2506 One-element structure load to two registers. 2507 2508 void ld1(const VRegister& vt, 2509 const VRegister& vt2, 2510 const MemOperand& src) 2511 2512 2513 ### LD1R ### 2514 2515 One-element single structure load to all lanes. 2516 2517 void ld1r(const VRegister& vt, 2518 const MemOperand& src) 2519 2520 2521 ### LD2 ### 2522 2523 Two-element single structure load to one lane. 2524 2525 void ld2(const VRegister& vt, 2526 const VRegister& vt2, 2527 int lane, 2528 const MemOperand& src) 2529 2530 2531 ### LD2 ### 2532 2533 Two-element structure load. 2534 2535 void ld2(const VRegister& vt, 2536 const VRegister& vt2, 2537 const MemOperand& src) 2538 2539 2540 ### LD2R ### 2541 2542 Two-element single structure load to all lanes. 2543 2544 void ld2r(const VRegister& vt, 2545 const VRegister& vt2, 2546 const MemOperand& src) 2547 2548 2549 ### LD3 ### 2550 2551 Three-element single structure load to one lane. 2552 2553 void ld3(const VRegister& vt, 2554 const VRegister& vt2, 2555 const VRegister& vt3, 2556 int lane, 2557 const MemOperand& src) 2558 2559 2560 ### LD3 ### 2561 2562 Three-element structure load. 2563 2564 void ld3(const VRegister& vt, 2565 const VRegister& vt2, 2566 const VRegister& vt3, 2567 const MemOperand& src) 2568 2569 2570 ### LD3R ### 2571 2572 Three-element single structure load to all lanes. 2573 2574 void ld3r(const VRegister& vt, 2575 const VRegister& vt2, 2576 const VRegister& vt3, 2577 const MemOperand& src) 2578 2579 2580 ### LD4 ### 2581 2582 Four-element single structure load to one lane. 2583 2584 void ld4(const VRegister& vt, 2585 const VRegister& vt2, 2586 const VRegister& vt3, 2587 const VRegister& vt4, 2588 int lane, 2589 const MemOperand& src) 2590 2591 2592 ### LD4 ### 2593 2594 Four-element structure load. 2595 2596 void ld4(const VRegister& vt, 2597 const VRegister& vt2, 2598 const VRegister& vt3, 2599 const VRegister& vt4, 2600 const MemOperand& src) 2601 2602 2603 ### LD4R ### 2604 2605 Four-element single structure load to all lanes. 2606 2607 void ld4r(const VRegister& vt, 2608 const VRegister& vt2, 2609 const VRegister& vt3, 2610 const VRegister& vt4, 2611 const MemOperand& src) 2612 2613 2614 ### MLA ### 2615 2616 Multiply-add by scalar element. 2617 2618 void mla(const VRegister& vd, 2619 const VRegister& vn, 2620 const VRegister& vm, 2621 int vm_index) 2622 2623 2624 ### MLA ### 2625 2626 Multiply-add to accumulator. 2627 2628 void mla(const VRegister& vd, 2629 const VRegister& vn, 2630 const VRegister& vm) 2631 2632 2633 ### MLS ### 2634 2635 Multiply-subtract by scalar element. 2636 2637 void mls(const VRegister& vd, 2638 const VRegister& vn, 2639 const VRegister& vm, 2640 int vm_index) 2641 2642 2643 ### MLS ### 2644 2645 Multiply-subtract to accumulator. 2646 2647 void mls(const VRegister& vd, 2648 const VRegister& vn, 2649 const VRegister& vm) 2650 2651 2652 ### MOV ### 2653 2654 Move general-purpose register to a vector element. 2655 2656 void mov(const VRegister& vd, 2657 int vd_index, 2658 const Register& rn) 2659 2660 2661 ### MOV ### 2662 2663 Move register to register. 2664 2665 void mov(const VRegister& vd, 2666 const VRegister& vn) 2667 2668 2669 ### MOV ### 2670 2671 Move vector element to another vector element. 2672 2673 void mov(const VRegister& vd, 2674 int vd_index, 2675 const VRegister& vn, 2676 int vn_index) 2677 2678 2679 ### MOV ### 2680 2681 Move vector element to general-purpose register. 2682 2683 void mov(const Register& rd, 2684 const VRegister& vn, 2685 int vn_index) 2686 2687 2688 ### MOV ### 2689 2690 Move vector element to scalar. 2691 2692 void mov(const VRegister& vd, 2693 const VRegister& vn, 2694 int vn_index) 2695 2696 2697 ### MOVI ### 2698 2699 Vector move immediate. 2700 2701 void movi(const VRegister& vd, 2702 const uint64_t imm, 2703 Shift shift = LSL, 2704 const int shift_amount = 0) 2705 2706 2707 ### MUL ### 2708 2709 Multiply by scalar element. 2710 2711 void mul(const VRegister& vd, 2712 const VRegister& vn, 2713 const VRegister& vm, 2714 int vm_index) 2715 2716 2717 ### MUL ### 2718 2719 Multiply. 2720 2721 void mul(const VRegister& vd, 2722 const VRegister& vn, 2723 const VRegister& vm) 2724 2725 2726 ### MVN ### 2727 2728 Bitwise not. 2729 2730 void mvn(const VRegister& vd, 2731 const VRegister& vn) 2732 2733 2734 ### MVNI ### 2735 2736 Vector move inverted immediate. 2737 2738 void mvni(const VRegister& vd, 2739 const int imm8, 2740 Shift shift = LSL, 2741 const int shift_amount = 0) 2742 2743 2744 ### NEG ### 2745 2746 Negate. 2747 2748 void neg(const VRegister& vd, 2749 const VRegister& vn) 2750 2751 2752 ### NOT ### 2753 2754 Bitwise not. 2755 2756 void not_(const VRegister& vd, 2757 const VRegister& vn) 2758 2759 2760 ### ORN ### 2761 2762 Bitwise orn. 2763 2764 void orn(const VRegister& vd, 2765 const VRegister& vn, 2766 const VRegister& vm) 2767 2768 2769 ### ORR ### 2770 2771 Bitwise or immediate. 2772 2773 void orr(const VRegister& vd, 2774 const int imm8, 2775 const int left_shift = 0) 2776 2777 2778 ### ORR ### 2779 2780 Bitwise or. 2781 2782 void orr(const VRegister& vd, 2783 const VRegister& vn, 2784 const VRegister& vm) 2785 2786 2787 ### PMUL ### 2788 2789 Polynomial multiply. 2790 2791 void pmul(const VRegister& vd, 2792 const VRegister& vn, 2793 const VRegister& vm) 2794 2795 2796 ### PMULL ### 2797 2798 Polynomial multiply long. 2799 2800 void pmull(const VRegister& vd, 2801 const VRegister& vn, 2802 const VRegister& vm) 2803 2804 2805 ### PMULL2 ### 2806 2807 Polynomial multiply long (second part). 2808 2809 void pmull2(const VRegister& vd, 2810 const VRegister& vn, 2811 const VRegister& vm) 2812 2813 2814 ### RADDHN ### 2815 2816 Rounding add narrow returning high half. 2817 2818 void raddhn(const VRegister& vd, 2819 const VRegister& vn, 2820 const VRegister& vm) 2821 2822 2823 ### RADDHN2 ### 2824 2825 Rounding add narrow returning high half (second part). 2826 2827 void raddhn2(const VRegister& vd, 2828 const VRegister& vn, 2829 const VRegister& vm) 2830 2831 2832 ### RBIT ### 2833 2834 Reverse bit order. 2835 2836 void rbit(const VRegister& vd, 2837 const VRegister& vn) 2838 2839 2840 ### REV16 ### 2841 2842 Reverse elements in 16-bit halfwords. 2843 2844 void rev16(const VRegister& vd, 2845 const VRegister& vn) 2846 2847 2848 ### REV32 ### 2849 2850 Reverse elements in 32-bit words. 2851 2852 void rev32(const VRegister& vd, 2853 const VRegister& vn) 2854 2855 2856 ### REV64 ### 2857 2858 Reverse elements in 64-bit doublewords. 2859 2860 void rev64(const VRegister& vd, 2861 const VRegister& vn) 2862 2863 2864 ### RSHRN ### 2865 2866 Rounding shift right narrow by immediate. 2867 2868 void rshrn(const VRegister& vd, 2869 const VRegister& vn, 2870 int shift) 2871 2872 2873 ### RSHRN2 ### 2874 2875 Rounding shift right narrow by immediate (second part). 2876 2877 void rshrn2(const VRegister& vd, 2878 const VRegister& vn, 2879 int shift) 2880 2881 2882 ### RSUBHN ### 2883 2884 Rounding subtract narrow returning high half. 2885 2886 void rsubhn(const VRegister& vd, 2887 const VRegister& vn, 2888 const VRegister& vm) 2889 2890 2891 ### RSUBHN2 ### 2892 2893 Rounding subtract narrow returning high half (second part). 2894 2895 void rsubhn2(const VRegister& vd, 2896 const VRegister& vn, 2897 const VRegister& vm) 2898 2899 2900 ### SABA ### 2901 2902 Signed absolute difference and accumulate. 2903 2904 void saba(const VRegister& vd, 2905 const VRegister& vn, 2906 const VRegister& vm) 2907 2908 2909 ### SABAL ### 2910 2911 Signed absolute difference and accumulate long. 2912 2913 void sabal(const VRegister& vd, 2914 const VRegister& vn, 2915 const VRegister& vm) 2916 2917 2918 ### SABAL2 ### 2919 2920 Signed absolute difference and accumulate long (second part). 2921 2922 void sabal2(const VRegister& vd, 2923 const VRegister& vn, 2924 const VRegister& vm) 2925 2926 2927 ### SABD ### 2928 2929 Signed absolute difference. 2930 2931 void sabd(const VRegister& vd, 2932 const VRegister& vn, 2933 const VRegister& vm) 2934 2935 2936 ### SABDL ### 2937 2938 Signed absolute difference long. 2939 2940 void sabdl(const VRegister& vd, 2941 const VRegister& vn, 2942 const VRegister& vm) 2943 2944 2945 ### SABDL2 ### 2946 2947 Signed absolute difference long (second part). 2948 2949 void sabdl2(const VRegister& vd, 2950 const VRegister& vn, 2951 const VRegister& vm) 2952 2953 2954 ### SADALP ### 2955 2956 Signed pairwise long add and accumulate. 2957 2958 void sadalp(const VRegister& vd, 2959 const VRegister& vn) 2960 2961 2962 ### SADDL ### 2963 2964 Signed add long. 2965 2966 void saddl(const VRegister& vd, 2967 const VRegister& vn, 2968 const VRegister& vm) 2969 2970 2971 ### SADDL2 ### 2972 2973 Signed add long (second part). 2974 2975 void saddl2(const VRegister& vd, 2976 const VRegister& vn, 2977 const VRegister& vm) 2978 2979 2980 ### SADDLP ### 2981 2982 Signed pairwise long add. 2983 2984 void saddlp(const VRegister& vd, 2985 const VRegister& vn) 2986 2987 2988 ### SADDLV ### 2989 2990 Signed add long across vector. 2991 2992 void saddlv(const VRegister& vd, 2993 const VRegister& vn) 2994 2995 2996 ### SADDW ### 2997 2998 Signed add wide. 2999 3000 void saddw(const VRegister& vd, 3001 const VRegister& vn, 3002 const VRegister& vm) 3003 3004 3005 ### SADDW2 ### 3006 3007 Signed add wide (second part). 3008 3009 void saddw2(const VRegister& vd, 3010 const VRegister& vn, 3011 const VRegister& vm) 3012 3013 3014 ### SCVTF ### 3015 3016 Convert signed integer or fixed point to FP. 3017 3018 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0) 3019 3020 3021 ### SCVTF ### 3022 3023 Convert signed integer or fixed-point to FP. 3024 3025 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 3026 3027 3028 ### SHADD ### 3029 3030 Signed halving add. 3031 3032 void shadd(const VRegister& vd, 3033 const VRegister& vn, 3034 const VRegister& vm) 3035 3036 3037 ### SHL ### 3038 3039 Shift left by immediate. 3040 3041 void shl(const VRegister& vd, 3042 const VRegister& vn, 3043 int shift) 3044 3045 3046 ### SHLL ### 3047 3048 Shift left long by element size. 3049 3050 void shll(const VRegister& vd, 3051 const VRegister& vn, 3052 int shift) 3053 3054 3055 ### SHLL2 ### 3056 3057 Shift left long by element size (second part). 3058 3059 void shll2(const VRegister& vd, 3060 const VRegister& vn, 3061 int shift) 3062 3063 3064 ### SHRN ### 3065 3066 Shift right narrow by immediate. 3067 3068 void shrn(const VRegister& vd, 3069 const VRegister& vn, 3070 int shift) 3071 3072 3073 ### SHRN2 ### 3074 3075 Shift right narrow by immediate (second part). 3076 3077 void shrn2(const VRegister& vd, 3078 const VRegister& vn, 3079 int shift) 3080 3081 3082 ### SHSUB ### 3083 3084 Signed halving sub. 3085 3086 void shsub(const VRegister& vd, 3087 const VRegister& vn, 3088 const VRegister& vm) 3089 3090 3091 ### SLI ### 3092 3093 Shift left by immediate and insert. 3094 3095 void sli(const VRegister& vd, 3096 const VRegister& vn, 3097 int shift) 3098 3099 3100 ### SMAX ### 3101 3102 Signed maximum. 3103 3104 void smax(const VRegister& vd, 3105 const VRegister& vn, 3106 const VRegister& vm) 3107 3108 3109 ### SMAXP ### 3110 3111 Signed pairwise maximum. 3112 3113 void smaxp(const VRegister& vd, 3114 const VRegister& vn, 3115 const VRegister& vm) 3116 3117 3118 ### SMAXV ### 3119 3120 Signed maximum across vector. 3121 3122 void smaxv(const VRegister& vd, 3123 const VRegister& vn) 3124 3125 3126 ### SMIN ### 3127 3128 Signed minimum. 3129 3130 void smin(const VRegister& vd, 3131 const VRegister& vn, 3132 const VRegister& vm) 3133 3134 3135 ### SMINP ### 3136 3137 Signed minimum pairwise. 3138 3139 void sminp(const VRegister& vd, 3140 const VRegister& vn, 3141 const VRegister& vm) 3142 3143 3144 ### SMINV ### 3145 3146 Signed minimum across vector. 3147 3148 void sminv(const VRegister& vd, 3149 const VRegister& vn) 3150 3151 3152 ### SMLAL ### 3153 3154 Signed long multiply-add by scalar element. 3155 3156 void smlal(const VRegister& vd, 3157 const VRegister& vn, 3158 const VRegister& vm, 3159 int vm_index) 3160 3161 3162 ### SMLAL ### 3163 3164 Signed long multiply-add. 3165 3166 void smlal(const VRegister& vd, 3167 const VRegister& vn, 3168 const VRegister& vm) 3169 3170 3171 ### SMLAL2 ### 3172 3173 Signed long multiply-add (second part). 3174 3175 void smlal2(const VRegister& vd, 3176 const VRegister& vn, 3177 const VRegister& vm) 3178 3179 3180 ### SMLAL2 ### 3181 3182 Signed long multiply-add by scalar element (second part). 3183 3184 void smlal2(const VRegister& vd, 3185 const VRegister& vn, 3186 const VRegister& vm, 3187 int vm_index) 3188 3189 3190 ### SMLSL ### 3191 3192 Signed long multiply-sub by scalar element. 3193 3194 void smlsl(const VRegister& vd, 3195 const VRegister& vn, 3196 const VRegister& vm, 3197 int vm_index) 3198 3199 3200 ### SMLSL ### 3201 3202 Signed long multiply-sub. 3203 3204 void smlsl(const VRegister& vd, 3205 const VRegister& vn, 3206 const VRegister& vm) 3207 3208 3209 ### SMLSL2 ### 3210 3211 Signed long multiply-sub (second part). 3212 3213 void smlsl2(const VRegister& vd, 3214 const VRegister& vn, 3215 const VRegister& vm) 3216 3217 3218 ### SMLSL2 ### 3219 3220 Signed long multiply-sub by scalar element (second part). 3221 3222 void smlsl2(const VRegister& vd, 3223 const VRegister& vn, 3224 const VRegister& vm, 3225 int vm_index) 3226 3227 3228 ### SMOV ### 3229 3230 Signed move vector element to general-purpose register. 3231 3232 void smov(const Register& rd, 3233 const VRegister& vn, 3234 int vn_index) 3235 3236 3237 ### SMULL ### 3238 3239 Signed long multiply by scalar element. 3240 3241 void smull(const VRegister& vd, 3242 const VRegister& vn, 3243 const VRegister& vm, 3244 int vm_index) 3245 3246 3247 ### SMULL ### 3248 3249 Signed long multiply. 3250 3251 void smull(const VRegister& vd, 3252 const VRegister& vn, 3253 const VRegister& vm) 3254 3255 3256 ### SMULL2 ### 3257 3258 Signed long multiply (second part). 3259 3260 void smull2(const VRegister& vd, 3261 const VRegister& vn, 3262 const VRegister& vm) 3263 3264 3265 ### SMULL2 ### 3266 3267 Signed long multiply by scalar element (second part). 3268 3269 void smull2(const VRegister& vd, 3270 const VRegister& vn, 3271 const VRegister& vm, 3272 int vm_index) 3273 3274 3275 ### SQABS ### 3276 3277 Signed saturating absolute value. 3278 3279 void sqabs(const VRegister& vd, 3280 const VRegister& vn) 3281 3282 3283 ### SQADD ### 3284 3285 Signed saturating add. 3286 3287 void sqadd(const VRegister& vd, 3288 const VRegister& vn, 3289 const VRegister& vm) 3290 3291 3292 ### SQDMLAL ### 3293 3294 Signed saturating doubling long multiply-add by element. 3295 3296 void sqdmlal(const VRegister& vd, 3297 const VRegister& vn, 3298 const VRegister& vm, 3299 int vm_index) 3300 3301 3302 ### SQDMLAL ### 3303 3304 Signed saturating doubling long multiply-add. 3305 3306 void sqdmlal(const VRegister& vd, 3307 const VRegister& vn, 3308 const VRegister& vm) 3309 3310 3311 ### SQDMLAL2 ### 3312 3313 Signed saturating doubling long multiply-add (second part). 3314 3315 void sqdmlal2(const VRegister& vd, 3316 const VRegister& vn, 3317 const VRegister& vm) 3318 3319 3320 ### SQDMLAL2 ### 3321 3322 Signed saturating doubling long multiply-add by element (second part). 3323 3324 void sqdmlal2(const VRegister& vd, 3325 const VRegister& vn, 3326 const VRegister& vm, 3327 int vm_index) 3328 3329 3330 ### SQDMLSL ### 3331 3332 Signed saturating doubling long multiply-sub by element. 3333 3334 void sqdmlsl(const VRegister& vd, 3335 const VRegister& vn, 3336 const VRegister& vm, 3337 int vm_index) 3338 3339 3340 ### SQDMLSL ### 3341 3342 Signed saturating doubling long multiply-subtract. 3343 3344 void sqdmlsl(const VRegister& vd, 3345 const VRegister& vn, 3346 const VRegister& vm) 3347 3348 3349 ### SQDMLSL2 ### 3350 3351 Signed saturating doubling long multiply-sub by element (second part). 3352 3353 void sqdmlsl2(const VRegister& vd, 3354 const VRegister& vn, 3355 const VRegister& vm, 3356 int vm_index) 3357 3358 3359 ### SQDMLSL2 ### 3360 3361 Signed saturating doubling long multiply-subtract (second part). 3362 3363 void sqdmlsl2(const VRegister& vd, 3364 const VRegister& vn, 3365 const VRegister& vm) 3366 3367 3368 ### SQDMULH ### 3369 3370 Signed saturating doubling multiply element returning high half. 3371 3372 void sqdmulh(const VRegister& vd, 3373 const VRegister& vn, 3374 const VRegister& vm, 3375 int vm_index) 3376 3377 3378 ### SQDMULH ### 3379 3380 Signed saturating doubling multiply returning high half. 3381 3382 void sqdmulh(const VRegister& vd, 3383 const VRegister& vn, 3384 const VRegister& vm) 3385 3386 3387 ### SQDMULL ### 3388 3389 Signed saturating double long multiply by element. 3390 3391 void sqdmull(const VRegister& vd, 3392 const VRegister& vn, 3393 const VRegister& vm, 3394 int vm_index) 3395 3396 3397 ### SQDMULL ### 3398 3399 Signed saturating doubling long multiply. 3400 3401 void sqdmull(const VRegister& vd, 3402 const VRegister& vn, 3403 const VRegister& vm) 3404 3405 3406 ### SQDMULL2 ### 3407 3408 Signed saturating double long multiply by element (second part). 3409 3410 void sqdmull2(const VRegister& vd, 3411 const VRegister& vn, 3412 const VRegister& vm, 3413 int vm_index) 3414 3415 3416 ### SQDMULL2 ### 3417 3418 Signed saturating doubling long multiply (second part). 3419 3420 void sqdmull2(const VRegister& vd, 3421 const VRegister& vn, 3422 const VRegister& vm) 3423 3424 3425 ### SQNEG ### 3426 3427 Signed saturating negate. 3428 3429 void sqneg(const VRegister& vd, 3430 const VRegister& vn) 3431 3432 3433 ### SQRDMULH ### 3434 3435 Signed saturating rounding doubling multiply element returning high half. 3436 3437 void sqrdmulh(const VRegister& vd, 3438 const VRegister& vn, 3439 const VRegister& vm, 3440 int vm_index) 3441 3442 3443 ### SQRDMULH ### 3444 3445 Signed saturating rounding doubling multiply returning high half. 3446 3447 void sqrdmulh(const VRegister& vd, 3448 const VRegister& vn, 3449 const VRegister& vm) 3450 3451 3452 ### SQRSHL ### 3453 3454 Signed saturating rounding shift left by register. 3455 3456 void sqrshl(const VRegister& vd, 3457 const VRegister& vn, 3458 const VRegister& vm) 3459 3460 3461 ### SQRSHRN ### 3462 3463 Signed saturating rounded shift right narrow by immediate. 3464 3465 void sqrshrn(const VRegister& vd, 3466 const VRegister& vn, 3467 int shift) 3468 3469 3470 ### SQRSHRN2 ### 3471 3472 Signed saturating rounded shift right narrow by immediate (second part). 3473 3474 void sqrshrn2(const VRegister& vd, 3475 const VRegister& vn, 3476 int shift) 3477 3478 3479 ### SQRSHRUN ### 3480 3481 Signed sat rounded shift right unsigned narrow by immediate. 3482 3483 void sqrshrun(const VRegister& vd, 3484 const VRegister& vn, 3485 int shift) 3486 3487 3488 ### SQRSHRUN2 ### 3489 3490 Signed sat rounded shift right unsigned narrow by immediate (second part). 3491 3492 void sqrshrun2(const VRegister& vd, 3493 const VRegister& vn, 3494 int shift) 3495 3496 3497 ### SQSHL ### 3498 3499 Signed saturating shift left by immediate. 3500 3501 void sqshl(const VRegister& vd, 3502 const VRegister& vn, 3503 int shift) 3504 3505 3506 ### SQSHL ### 3507 3508 Signed saturating shift left by register. 3509 3510 void sqshl(const VRegister& vd, 3511 const VRegister& vn, 3512 const VRegister& vm) 3513 3514 3515 ### SQSHLU ### 3516 3517 Signed saturating shift left unsigned by immediate. 3518 3519 void sqshlu(const VRegister& vd, 3520 const VRegister& vn, 3521 int shift) 3522 3523 3524 ### SQSHRN ### 3525 3526 Signed saturating shift right narrow by immediate. 3527 3528 void sqshrn(const VRegister& vd, 3529 const VRegister& vn, 3530 int shift) 3531 3532 3533 ### SQSHRN2 ### 3534 3535 Signed saturating shift right narrow by immediate (second part). 3536 3537 void sqshrn2(const VRegister& vd, 3538 const VRegister& vn, 3539 int shift) 3540 3541 3542 ### SQSHRUN ### 3543 3544 Signed saturating shift right unsigned narrow by immediate. 3545 3546 void sqshrun(const VRegister& vd, 3547 const VRegister& vn, 3548 int shift) 3549 3550 3551 ### SQSHRUN2 ### 3552 3553 Signed saturating shift right unsigned narrow by immediate (second part). 3554 3555 void sqshrun2(const VRegister& vd, 3556 const VRegister& vn, 3557 int shift) 3558 3559 3560 ### SQSUB ### 3561 3562 Signed saturating subtract. 3563 3564 void sqsub(const VRegister& vd, 3565 const VRegister& vn, 3566 const VRegister& vm) 3567 3568 3569 ### SQXTN ### 3570 3571 Signed saturating extract narrow. 3572 3573 void sqxtn(const VRegister& vd, 3574 const VRegister& vn) 3575 3576 3577 ### SQXTN2 ### 3578 3579 Signed saturating extract narrow (second part). 3580 3581 void sqxtn2(const VRegister& vd, 3582 const VRegister& vn) 3583 3584 3585 ### SQXTUN ### 3586 3587 Signed saturating extract unsigned narrow. 3588 3589 void sqxtun(const VRegister& vd, 3590 const VRegister& vn) 3591 3592 3593 ### SQXTUN2 ### 3594 3595 Signed saturating extract unsigned narrow (second part). 3596 3597 void sqxtun2(const VRegister& vd, 3598 const VRegister& vn) 3599 3600 3601 ### SRHADD ### 3602 3603 Signed rounding halving add. 3604 3605 void srhadd(const VRegister& vd, 3606 const VRegister& vn, 3607 const VRegister& vm) 3608 3609 3610 ### SRI ### 3611 3612 Shift right by immediate and insert. 3613 3614 void sri(const VRegister& vd, 3615 const VRegister& vn, 3616 int shift) 3617 3618 3619 ### SRSHL ### 3620 3621 Signed rounding shift left by register. 3622 3623 void srshl(const VRegister& vd, 3624 const VRegister& vn, 3625 const VRegister& vm) 3626 3627 3628 ### SRSHR ### 3629 3630 Signed rounding shift right by immediate. 3631 3632 void srshr(const VRegister& vd, 3633 const VRegister& vn, 3634 int shift) 3635 3636 3637 ### SRSRA ### 3638 3639 Signed rounding shift right by immediate and accumulate. 3640 3641 void srsra(const VRegister& vd, 3642 const VRegister& vn, 3643 int shift) 3644 3645 3646 ### SSHL ### 3647 3648 Signed shift left by register. 3649 3650 void sshl(const VRegister& vd, 3651 const VRegister& vn, 3652 const VRegister& vm) 3653 3654 3655 ### SSHLL ### 3656 3657 Signed shift left long by immediate. 3658 3659 void sshll(const VRegister& vd, 3660 const VRegister& vn, 3661 int shift) 3662 3663 3664 ### SSHLL2 ### 3665 3666 Signed shift left long by immediate (second part). 3667 3668 void sshll2(const VRegister& vd, 3669 const VRegister& vn, 3670 int shift) 3671 3672 3673 ### SSHR ### 3674 3675 Signed shift right by immediate. 3676 3677 void sshr(const VRegister& vd, 3678 const VRegister& vn, 3679 int shift) 3680 3681 3682 ### SSRA ### 3683 3684 Signed shift right by immediate and accumulate. 3685 3686 void ssra(const VRegister& vd, 3687 const VRegister& vn, 3688 int shift) 3689 3690 3691 ### SSUBL ### 3692 3693 Signed subtract long. 3694 3695 void ssubl(const VRegister& vd, 3696 const VRegister& vn, 3697 const VRegister& vm) 3698 3699 3700 ### SSUBL2 ### 3701 3702 Signed subtract long (second part). 3703 3704 void ssubl2(const VRegister& vd, 3705 const VRegister& vn, 3706 const VRegister& vm) 3707 3708 3709 ### SSUBW ### 3710 3711 Signed integer subtract wide. 3712 3713 void ssubw(const VRegister& vd, 3714 const VRegister& vn, 3715 const VRegister& vm) 3716 3717 3718 ### SSUBW2 ### 3719 3720 Signed integer subtract wide (second part). 3721 3722 void ssubw2(const VRegister& vd, 3723 const VRegister& vn, 3724 const VRegister& vm) 3725 3726 3727 ### ST1 ### 3728 3729 One-element single structure store from one lane. 3730 3731 void st1(const VRegister& vt, 3732 int lane, 3733 const MemOperand& src) 3734 3735 3736 ### ST1 ### 3737 3738 One-element structure store from four registers. 3739 3740 void st1(const VRegister& vt, 3741 const VRegister& vt2, 3742 const VRegister& vt3, 3743 const VRegister& vt4, 3744 const MemOperand& src) 3745 3746 3747 ### ST1 ### 3748 3749 One-element structure store from one register. 3750 3751 void st1(const VRegister& vt, 3752 const MemOperand& src) 3753 3754 3755 ### ST1 ### 3756 3757 One-element structure store from three registers. 3758 3759 void st1(const VRegister& vt, 3760 const VRegister& vt2, 3761 const VRegister& vt3, 3762 const MemOperand& src) 3763 3764 3765 ### ST1 ### 3766 3767 One-element structure store from two registers. 3768 3769 void st1(const VRegister& vt, 3770 const VRegister& vt2, 3771 const MemOperand& src) 3772 3773 3774 ### ST2 ### 3775 3776 Two-element single structure store from two lanes. 3777 3778 void st2(const VRegister& vt, 3779 const VRegister& vt2, 3780 int lane, 3781 const MemOperand& src) 3782 3783 3784 ### ST2 ### 3785 3786 Two-element structure store from two registers. 3787 3788 void st2(const VRegister& vt, 3789 const VRegister& vt2, 3790 const MemOperand& src) 3791 3792 3793 ### ST3 ### 3794 3795 Three-element single structure store from three lanes. 3796 3797 void st3(const VRegister& vt, 3798 const VRegister& vt2, 3799 const VRegister& vt3, 3800 int lane, 3801 const MemOperand& src) 3802 3803 3804 ### ST3 ### 3805 3806 Three-element structure store from three registers. 3807 3808 void st3(const VRegister& vt, 3809 const VRegister& vt2, 3810 const VRegister& vt3, 3811 const MemOperand& src) 3812 3813 3814 ### ST4 ### 3815 3816 Four-element single structure store from four lanes. 3817 3818 void st4(const VRegister& vt, 3819 const VRegister& vt2, 3820 const VRegister& vt3, 3821 const VRegister& vt4, 3822 int lane, 3823 const MemOperand& src) 3824 3825 3826 ### ST4 ### 3827 3828 Four-element structure store from four registers. 3829 3830 void st4(const VRegister& vt, 3831 const VRegister& vt2, 3832 const VRegister& vt3, 3833 const VRegister& vt4, 3834 const MemOperand& src) 3835 3836 3837 ### SUB ### 3838 3839 Subtract. 3840 3841 void sub(const VRegister& vd, 3842 const VRegister& vn, 3843 const VRegister& vm) 3844 3845 3846 ### SUBHN ### 3847 3848 Subtract narrow returning high half. 3849 3850 void subhn(const VRegister& vd, 3851 const VRegister& vn, 3852 const VRegister& vm) 3853 3854 3855 ### SUBHN2 ### 3856 3857 Subtract narrow returning high half (second part). 3858 3859 void subhn2(const VRegister& vd, 3860 const VRegister& vn, 3861 const VRegister& vm) 3862 3863 3864 ### SUQADD ### 3865 3866 Signed saturating accumulate of unsigned value. 3867 3868 void suqadd(const VRegister& vd, 3869 const VRegister& vn) 3870 3871 3872 ### SXTL ### 3873 3874 Signed extend long. 3875 3876 void sxtl(const VRegister& vd, 3877 const VRegister& vn) 3878 3879 3880 ### SXTL2 ### 3881 3882 Signed extend long (second part). 3883 3884 void sxtl2(const VRegister& vd, 3885 const VRegister& vn) 3886 3887 3888 ### TBL ### 3889 3890 Table lookup from four registers. 3891 3892 void tbl(const VRegister& vd, 3893 const VRegister& vn, 3894 const VRegister& vn2, 3895 const VRegister& vn3, 3896 const VRegister& vn4, 3897 const VRegister& vm) 3898 3899 3900 ### TBL ### 3901 3902 Table lookup from one register. 3903 3904 void tbl(const VRegister& vd, 3905 const VRegister& vn, 3906 const VRegister& vm) 3907 3908 3909 ### TBL ### 3910 3911 Table lookup from three registers. 3912 3913 void tbl(const VRegister& vd, 3914 const VRegister& vn, 3915 const VRegister& vn2, 3916 const VRegister& vn3, 3917 const VRegister& vm) 3918 3919 3920 ### TBL ### 3921 3922 Table lookup from two registers. 3923 3924 void tbl(const VRegister& vd, 3925 const VRegister& vn, 3926 const VRegister& vn2, 3927 const VRegister& vm) 3928 3929 3930 ### TBX ### 3931 3932 Table lookup extension from four registers. 3933 3934 void tbx(const VRegister& vd, 3935 const VRegister& vn, 3936 const VRegister& vn2, 3937 const VRegister& vn3, 3938 const VRegister& vn4, 3939 const VRegister& vm) 3940 3941 3942 ### TBX ### 3943 3944 Table lookup extension from one register. 3945 3946 void tbx(const VRegister& vd, 3947 const VRegister& vn, 3948 const VRegister& vm) 3949 3950 3951 ### TBX ### 3952 3953 Table lookup extension from three registers. 3954 3955 void tbx(const VRegister& vd, 3956 const VRegister& vn, 3957 const VRegister& vn2, 3958 const VRegister& vn3, 3959 const VRegister& vm) 3960 3961 3962 ### TBX ### 3963 3964 Table lookup extension from two registers. 3965 3966 void tbx(const VRegister& vd, 3967 const VRegister& vn, 3968 const VRegister& vn2, 3969 const VRegister& vm) 3970 3971 3972 ### TRN1 ### 3973 3974 Transpose vectors (primary). 3975 3976 void trn1(const VRegister& vd, 3977 const VRegister& vn, 3978 const VRegister& vm) 3979 3980 3981 ### TRN2 ### 3982 3983 Transpose vectors (secondary). 3984 3985 void trn2(const VRegister& vd, 3986 const VRegister& vn, 3987 const VRegister& vm) 3988 3989 3990 ### UABA ### 3991 3992 Unsigned absolute difference and accumulate. 3993 3994 void uaba(const VRegister& vd, 3995 const VRegister& vn, 3996 const VRegister& vm) 3997 3998 3999 ### UABAL ### 4000 4001 Unsigned absolute difference and accumulate long. 4002 4003 void uabal(const VRegister& vd, 4004 const VRegister& vn, 4005 const VRegister& vm) 4006 4007 4008 ### UABAL2 ### 4009 4010 Unsigned absolute difference and accumulate long (second part). 4011 4012 void uabal2(const VRegister& vd, 4013 const VRegister& vn, 4014 const VRegister& vm) 4015 4016 4017 ### UABD ### 4018 4019 Unsigned absolute difference. 4020 4021 void uabd(const VRegister& vd, 4022 const VRegister& vn, 4023 const VRegister& vm) 4024 4025 4026 ### UABDL ### 4027 4028 Unsigned absolute difference long. 4029 4030 void uabdl(const VRegister& vd, 4031 const VRegister& vn, 4032 const VRegister& vm) 4033 4034 4035 ### UABDL2 ### 4036 4037 Unsigned absolute difference long (second part). 4038 4039 void uabdl2(const VRegister& vd, 4040 const VRegister& vn, 4041 const VRegister& vm) 4042 4043 4044 ### UADALP ### 4045 4046 Unsigned pairwise long add and accumulate. 4047 4048 void uadalp(const VRegister& vd, 4049 const VRegister& vn) 4050 4051 4052 ### UADDL ### 4053 4054 Unsigned add long. 4055 4056 void uaddl(const VRegister& vd, 4057 const VRegister& vn, 4058 const VRegister& vm) 4059 4060 4061 ### UADDL2 ### 4062 4063 Unsigned add long (second part). 4064 4065 void uaddl2(const VRegister& vd, 4066 const VRegister& vn, 4067 const VRegister& vm) 4068 4069 4070 ### UADDLP ### 4071 4072 Unsigned pairwise long add. 4073 4074 void uaddlp(const VRegister& vd, 4075 const VRegister& vn) 4076 4077 4078 ### UADDLV ### 4079 4080 Unsigned add long across vector. 4081 4082 void uaddlv(const VRegister& vd, 4083 const VRegister& vn) 4084 4085 4086 ### UADDW ### 4087 4088 Unsigned add wide. 4089 4090 void uaddw(const VRegister& vd, 4091 const VRegister& vn, 4092 const VRegister& vm) 4093 4094 4095 ### UADDW2 ### 4096 4097 Unsigned add wide (second part). 4098 4099 void uaddw2(const VRegister& vd, 4100 const VRegister& vn, 4101 const VRegister& vm) 4102 4103 4104 ### UCVTF ### 4105 4106 Convert unsigned integer or fixed point to FP. 4107 4108 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0) 4109 4110 4111 ### UCVTF ### 4112 4113 Convert unsigned integer or fixed-point to FP. 4114 4115 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0) 4116 4117 4118 ### UHADD ### 4119 4120 Unsigned halving add. 4121 4122 void uhadd(const VRegister& vd, 4123 const VRegister& vn, 4124 const VRegister& vm) 4125 4126 4127 ### UHSUB ### 4128 4129 Unsigned halving sub. 4130 4131 void uhsub(const VRegister& vd, 4132 const VRegister& vn, 4133 const VRegister& vm) 4134 4135 4136 ### UMAX ### 4137 4138 Unsigned maximum. 4139 4140 void umax(const VRegister& vd, 4141 const VRegister& vn, 4142 const VRegister& vm) 4143 4144 4145 ### UMAXP ### 4146 4147 Unsigned pairwise maximum. 4148 4149 void umaxp(const VRegister& vd, 4150 const VRegister& vn, 4151 const VRegister& vm) 4152 4153 4154 ### UMAXV ### 4155 4156 Unsigned maximum across vector. 4157 4158 void umaxv(const VRegister& vd, 4159 const VRegister& vn) 4160 4161 4162 ### UMIN ### 4163 4164 Unsigned minimum. 4165 4166 void umin(const VRegister& vd, 4167 const VRegister& vn, 4168 const VRegister& vm) 4169 4170 4171 ### UMINP ### 4172 4173 Unsigned pairwise minimum. 4174 4175 void uminp(const VRegister& vd, 4176 const VRegister& vn, 4177 const VRegister& vm) 4178 4179 4180 ### UMINV ### 4181 4182 Unsigned minimum across vector. 4183 4184 void uminv(const VRegister& vd, 4185 const VRegister& vn) 4186 4187 4188 ### UMLAL ### 4189 4190 Unsigned long multiply-add by scalar element. 4191 4192 void umlal(const VRegister& vd, 4193 const VRegister& vn, 4194 const VRegister& vm, 4195 int vm_index) 4196 4197 4198 ### UMLAL ### 4199 4200 Unsigned long multiply-add. 4201 4202 void umlal(const VRegister& vd, 4203 const VRegister& vn, 4204 const VRegister& vm) 4205 4206 4207 ### UMLAL2 ### 4208 4209 Unsigned long multiply-add (second part). 4210 4211 void umlal2(const VRegister& vd, 4212 const VRegister& vn, 4213 const VRegister& vm) 4214 4215 4216 ### UMLAL2 ### 4217 4218 Unsigned long multiply-add by scalar element (second part). 4219 4220 void umlal2(const VRegister& vd, 4221 const VRegister& vn, 4222 const VRegister& vm, 4223 int vm_index) 4224 4225 4226 ### UMLSL ### 4227 4228 Unsigned long multiply-sub by scalar element. 4229 4230 void umlsl(const VRegister& vd, 4231 const VRegister& vn, 4232 const VRegister& vm, 4233 int vm_index) 4234 4235 4236 ### UMLSL ### 4237 4238 Unsigned long multiply-sub. 4239 4240 void umlsl(const VRegister& vd, 4241 const VRegister& vn, 4242 const VRegister& vm) 4243 4244 4245 ### UMLSL2 ### 4246 4247 Unsigned long multiply-sub (second part). 4248 4249 void umlsl2(const VRegister& vd, 4250 const VRegister& vn, 4251 const VRegister& vm) 4252 4253 4254 ### UMLSL2 ### 4255 4256 Unsigned long multiply-sub by scalar element (second part). 4257 4258 void umlsl2(const VRegister& vd, 4259 const VRegister& vn, 4260 const VRegister& vm, 4261 int vm_index) 4262 4263 4264 ### UMOV ### 4265 4266 Unsigned move vector element to general-purpose register. 4267 4268 void umov(const Register& rd, 4269 const VRegister& vn, 4270 int vn_index) 4271 4272 4273 ### UMULL ### 4274 4275 Unsigned long multiply by scalar element. 4276 4277 void umull(const VRegister& vd, 4278 const VRegister& vn, 4279 const VRegister& vm, 4280 int vm_index) 4281 4282 4283 ### UMULL ### 4284 4285 Unsigned long multiply long. 4286 4287 void umull(const VRegister& vd, 4288 const VRegister& vn, 4289 const VRegister& vm) 4290 4291 4292 ### UMULL2 ### 4293 4294 Unsigned long multiply (second part). 4295 4296 void umull2(const VRegister& vd, 4297 const VRegister& vn, 4298 const VRegister& vm) 4299 4300 4301 ### UMULL2 ### 4302 4303 Unsigned long multiply by scalar element (second part). 4304 4305 void umull2(const VRegister& vd, 4306 const VRegister& vn, 4307 const VRegister& vm, 4308 int vm_index) 4309 4310 4311 ### UQADD ### 4312 4313 Unsigned saturating add. 4314 4315 void uqadd(const VRegister& vd, 4316 const VRegister& vn, 4317 const VRegister& vm) 4318 4319 4320 ### UQRSHL ### 4321 4322 Unsigned saturating rounding shift left by register. 4323 4324 void uqrshl(const VRegister& vd, 4325 const VRegister& vn, 4326 const VRegister& vm) 4327 4328 4329 ### UQRSHRN ### 4330 4331 Unsigned saturating rounding shift right narrow by immediate. 4332 4333 void uqrshrn(const VRegister& vd, 4334 const VRegister& vn, 4335 int shift) 4336 4337 4338 ### UQRSHRN2 ### 4339 4340 Unsigned saturating rounding shift right narrow by immediate (second part). 4341 4342 void uqrshrn2(const VRegister& vd, 4343 const VRegister& vn, 4344 int shift) 4345 4346 4347 ### UQSHL ### 4348 4349 Unsigned saturating shift left by immediate. 4350 4351 void uqshl(const VRegister& vd, 4352 const VRegister& vn, 4353 int shift) 4354 4355 4356 ### UQSHL ### 4357 4358 Unsigned saturating shift left by register. 4359 4360 void uqshl(const VRegister& vd, 4361 const VRegister& vn, 4362 const VRegister& vm) 4363 4364 4365 ### UQSHRN ### 4366 4367 Unsigned saturating shift right narrow by immediate. 4368 4369 void uqshrn(const VRegister& vd, 4370 const VRegister& vn, 4371 int shift) 4372 4373 4374 ### UQSHRN2 ### 4375 4376 Unsigned saturating shift right narrow by immediate (second part). 4377 4378 void uqshrn2(const VRegister& vd, 4379 const VRegister& vn, 4380 int shift) 4381 4382 4383 ### UQSUB ### 4384 4385 Unsigned saturating subtract. 4386 4387 void uqsub(const VRegister& vd, 4388 const VRegister& vn, 4389 const VRegister& vm) 4390 4391 4392 ### UQXTN ### 4393 4394 Unsigned saturating extract narrow. 4395 4396 void uqxtn(const VRegister& vd, 4397 const VRegister& vn) 4398 4399 4400 ### UQXTN2 ### 4401 4402 Unsigned saturating extract narrow (second part). 4403 4404 void uqxtn2(const VRegister& vd, 4405 const VRegister& vn) 4406 4407 4408 ### URECPE ### 4409 4410 Unsigned reciprocal estimate. 4411 4412 void urecpe(const VRegister& vd, 4413 const VRegister& vn) 4414 4415 4416 ### URHADD ### 4417 4418 Unsigned rounding halving add. 4419 4420 void urhadd(const VRegister& vd, 4421 const VRegister& vn, 4422 const VRegister& vm) 4423 4424 4425 ### URSHL ### 4426 4427 Unsigned rounding shift left by register. 4428 4429 void urshl(const VRegister& vd, 4430 const VRegister& vn, 4431 const VRegister& vm) 4432 4433 4434 ### URSHR ### 4435 4436 Unsigned rounding shift right by immediate. 4437 4438 void urshr(const VRegister& vd, 4439 const VRegister& vn, 4440 int shift) 4441 4442 4443 ### URSQRTE ### 4444 4445 Unsigned reciprocal square root estimate. 4446 4447 void ursqrte(const VRegister& vd, 4448 const VRegister& vn) 4449 4450 4451 ### URSRA ### 4452 4453 Unsigned rounding shift right by immediate and accumulate. 4454 4455 void ursra(const VRegister& vd, 4456 const VRegister& vn, 4457 int shift) 4458 4459 4460 ### USHL ### 4461 4462 Unsigned shift left by register. 4463 4464 void ushl(const VRegister& vd, 4465 const VRegister& vn, 4466 const VRegister& vm) 4467 4468 4469 ### USHLL ### 4470 4471 Unsigned shift left long by immediate. 4472 4473 void ushll(const VRegister& vd, 4474 const VRegister& vn, 4475 int shift) 4476 4477 4478 ### USHLL2 ### 4479 4480 Unsigned shift left long by immediate (second part). 4481 4482 void ushll2(const VRegister& vd, 4483 const VRegister& vn, 4484 int shift) 4485 4486 4487 ### USHR ### 4488 4489 Unsigned shift right by immediate. 4490 4491 void ushr(const VRegister& vd, 4492 const VRegister& vn, 4493 int shift) 4494 4495 4496 ### USQADD ### 4497 4498 Unsigned saturating accumulate of signed value. 4499 4500 void usqadd(const VRegister& vd, 4501 const VRegister& vn) 4502 4503 4504 ### USRA ### 4505 4506 Unsigned shift right by immediate and accumulate. 4507 4508 void usra(const VRegister& vd, 4509 const VRegister& vn, 4510 int shift) 4511 4512 4513 ### USUBL ### 4514 4515 Unsigned subtract long. 4516 4517 void usubl(const VRegister& vd, 4518 const VRegister& vn, 4519 const VRegister& vm) 4520 4521 4522 ### USUBL2 ### 4523 4524 Unsigned subtract long (second part). 4525 4526 void usubl2(const VRegister& vd, 4527 const VRegister& vn, 4528 const VRegister& vm) 4529 4530 4531 ### USUBW ### 4532 4533 Unsigned subtract wide. 4534 4535 void usubw(const VRegister& vd, 4536 const VRegister& vn, 4537 const VRegister& vm) 4538 4539 4540 ### USUBW2 ### 4541 4542 Unsigned subtract wide (second part). 4543 4544 void usubw2(const VRegister& vd, 4545 const VRegister& vn, 4546 const VRegister& vm) 4547 4548 4549 ### UXTL ### 4550 4551 Unsigned extend long. 4552 4553 void uxtl(const VRegister& vd, 4554 const VRegister& vn) 4555 4556 4557 ### UXTL2 ### 4558 4559 Unsigned extend long (second part). 4560 4561 void uxtl2(const VRegister& vd, 4562 const VRegister& vn) 4563 4564 4565 ### UZP1 ### 4566 4567 Unzip vectors (primary). 4568 4569 void uzp1(const VRegister& vd, 4570 const VRegister& vn, 4571 const VRegister& vm) 4572 4573 4574 ### UZP2 ### 4575 4576 Unzip vectors (secondary). 4577 4578 void uzp2(const VRegister& vd, 4579 const VRegister& vn, 4580 const VRegister& vm) 4581 4582 4583 ### XTN ### 4584 4585 Extract narrow. 4586 4587 void xtn(const VRegister& vd, 4588 const VRegister& vn) 4589 4590 4591 ### XTN2 ### 4592 4593 Extract narrow (second part). 4594 4595 void xtn2(const VRegister& vd, 4596 const VRegister& vn) 4597 4598 4599 ### ZIP1 ### 4600 4601 Zip vectors (primary). 4602 4603 void zip1(const VRegister& vd, 4604 const VRegister& vn, 4605 const VRegister& vm) 4606 4607 4608 ### ZIP2 ### 4609 4610 Zip vectors (secondary). 4611 4612 void zip2(const VRegister& vd, 4613 const VRegister& vn, 4614 const VRegister& vm) 4615 4616 4617 4618 Additional or pseudo instructions 4619 --------------------------------- 4620 4621 ### BIND ### 4622 4623 Bind a label to the current PC. 4624 4625 void bind(Label* label) 4626 4627 4628 ### DC32 ### 4629 4630 Emit 32 bits of data into the instruction stream. 4631 4632 void dc32(uint32_t data) 4633 4634 4635 ### DC64 ### 4636 4637 Emit 64 bits of data into the instruction stream. 4638 4639 void dc64(uint64_t data) 4640 4641 4642 ### DCI ### 4643 4644 Emit raw instructions into the instruction stream. 4645 4646 void dci(Instr raw_inst) 4647 4648 4649 ### PLACE ### 4650 4651 Place a literal at the current PC. 4652 4653 void place(RawLiteral* literal) 4654 4655 4656 4657
