/external/llvm/unittests/IR/ |
ValueMapTest.cpp | 27 std::unique_ptr<BinaryOperator> AddV; 32 AddV(BinaryOperator::CreateAdd(ConstantV, ConstantV)) { 51 EXPECT_EQ(0u, VM.count(this->AddV.get())); 52 this->BitcastV->replaceAllUsesWith(this->AddV.get()); 53 EXPECT_EQ(7, VM.lookup(this->AddV.get())); 55 this->AddV.reset(); 56 EXPECT_EQ(0u, VM.count(this->AddV.get())); 76 EXPECT_TRUE(VM.find(this->AddV.get()) == VM.end()); 85 EXPECT_TRUE(CVM.find(this->AddV.get()) == CVM.end()); 89 VM.insert(std::make_pair(this->AddV.get(), 3)) [all...] |
/external/llvm/test/CodeGen/Mips/msa/ |
spill.ll | 76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1) 77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2) 78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3) 79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4) 80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5) 81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6) 82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7) 83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8) 84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9) 85 %r10 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r9, <16 x i8> %10 [all...] |
bitcast.ll | 9 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0) 11 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2) 18 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 19 ; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]] 25 ; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 26 ; BIGENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]] 33 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0) 35 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2) 42 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 43 ; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2] [all...] |
basic_operations.ll | 265 ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 284 ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 303 ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 319 ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 338 ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 356 ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]] 374 ; MIPS32-AE-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]] 390 ; MIPS32-AE-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]] 409 ; MIPS32-AE-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]] 433 ; MIPS32-AE-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1] [all...] |
3r-a.ll | 420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1) 425 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind 432 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]] 445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1) 450 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind 457 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]] 470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1) 475 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind 482 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]] 495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1 [all...] |
arithmetic.ll | 12 ; CHECK-DAG: addv.b [[R3:\$w[0-9]+]], [[R1]], [[R2]] 28 ; CHECK-DAG: addv.h [[R3:\$w[0-9]+]], [[R1]], [[R2]] 44 ; CHECK-DAG: addv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]] 60 ; CHECK-DAG: addv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
|
/external/clang/test/CodeGen/ |
aarch64-neon-across.c | 192 // CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.8b 198 // CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.4h 204 // CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.8b 210 // CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.4h 216 // CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b 222 // CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h 228 // CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s 234 // CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b 240 // CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h 246 // CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4 [all...] |
builtins-mips-msa.c | 78 v16i8_r = __builtin_msa_addv_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.addv.b( 79 v8i16_r = __builtin_msa_addv_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.addv.h( 80 v4i32_r = __builtin_msa_addv_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.addv.w( 81 v2i64_r = __builtin_msa_addv_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.addv.d( 83 v16u8_r = __builtin_msa_addv_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.addv.b( 84 v8u16_r = __builtin_msa_addv_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.addv.h( 85 v4u32_r = __builtin_msa_addv_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.addv.w( 86 v2u64_r = __builtin_msa_addv_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.addv.d( [all...] |
/external/llvm/test/MC/AArch64/ |
neon-across.s | 81 addv b0, v1.8b 82 addv b0, v1.16b 83 addv h0, v1.4h 84 addv h0, v1.8h 85 addv s0, v1.4s 87 // CHECK: addv b0, v1.8b // encoding: [0x20,0xb8,0x31,0x0e] 88 // CHECK: addv b0, v1.16b // encoding: [0x20,0xb8,0x31,0x4e] 89 // CHECK: addv h0, v1.4h // encoding: [0x20,0xb8,0x71,0x0e] 90 // CHECK: addv h0, v1.8h // encoding: [0x20,0xb8,0x71,0x4e] 91 // CHECK: addv s0, v1.4s // encoding: [0x20,0xb8,0xb1,0x4e [all...] |
dot-req.s | 28 addv bob, v0.8b 34 // CHECK: addv b6, v0.8b // encoding: [0x06,0xb8,0x31,0x0e]
|
arm64-advsimd.s | 73 addv.8b b0, v0 74 addv.16b b0, v0 75 addv.4h h0, v0 76 addv.8h h0, v0 77 addv.4s s0, v0 79 ; CHECK: addv.8b b0, v0 ; encoding: [0x00,0xb8,0x31,0x0e] 80 ; CHECK: addv.16b b0, v0 ; encoding: [0x00,0xb8,0x31,0x4e] 81 ; CHECK: addv.4h h0, v0 ; encoding: [0x00,0xb8,0x71,0x0e] 82 ; CHECK: addv.8h h0, v0 ; encoding: [0x00,0xb8,0x71,0x4e] 83 ; CHECK: addv.4s s0, v0 ; encoding: [0x00,0xb8,0xb1,0x4e [all...] |
/external/llvm/test/CodeGen/AArch64/ |
arm64-vaddv.ll | 5 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 16 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1 28 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 39 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1 94 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 105 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1 117 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 128 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 139 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1 151 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v [all...] |
arm64-neon-across.ll | 343 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b 352 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h 361 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b 370 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h 379 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b 388 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h 397 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s 405 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b 414 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h 423 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4 [all...] |
/external/llvm/test/CodeGen/SystemZ/ |
int-add-16.ll | 17 %addv = bitcast i128 %add to <2 x i64> 18 %high = extractelement <2 x i64> %addv, i32 0 20 %low = extractelement <2 x i64> %addv, i32 1
|
/external/llvm/test/MC/Mips/msa/ |
test_3r.s | 19 # CHECK: addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e] 20 # CHECK: addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e] 21 # CHECK: addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce] 22 # CHECK: addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e] 262 addv.b $w24, $w20, $w21 263 addv.h $w4, $w13, $w27 264 addv.w $w19, $w11, $w14 265 addv.d $w2, $w21, $w31 [all...] |
/external/llvm/test/MC/Disassembler/Mips/msa/ |
test_3r.txt | 19 0x78 0x15 0xa6 0x0e # CHECK: addv.b $w24, $w20, $w21 20 0x78 0x3b 0x69 0x0e # CHECK: addv.h $w4, $w13, $w27 21 0x78 0x4e 0x5c 0xce # CHECK: addv.w $w19, $w11, $w14 22 0x78 0x7f 0xa8 0x8e # CHECK: addv.d $w2, $w21, $w31
|
/external/llvm/test/MC/Disassembler/AArch64/ |
arm64-advsimd.txt | 77 # CHECK: addv.8b b0, v0 78 # CHECK: addv.16b b0, v0 79 # CHECK: addv.4h h0, v0 80 # CHECK: addv.8h h0, v0 81 # CHECK: addv.4s s0, v0 [all...] |
/external/llvm/lib/Target/Mips/ |
MipsMSAInstrInfo.td | [all...] |
/external/valgrind/VEX/priv/ |
guest_amd64_toIR.c | [all...] |
/external/vixl/test/ |
test-simulator-traces-a64.h | 90 #include "traces/a64/sim-addv-b-16b-trace-a64.h" 91 #include "traces/a64/sim-addv-b-8b-trace-a64.h" 92 #include "traces/a64/sim-addv-h-4h-trace-a64.h" 93 #include "traces/a64/sim-addv-h-8h-trace-a64.h" 94 #include "traces/a64/sim-addv-s-4s-trace-a64.h" [all...] |
test-disasm-a64.cc | [all...] |
/external/valgrind/none/tests/arm64/ |
fp_and_simd.c | [all...] |
/external/vixl/doc/ |
supported-instructions.md | 1454 ### ADDV ### 1458 void addv(const VRegister& vd, [all...] |
/external/vixl/src/vixl/a64/ |
macro-assembler-a64.h | [all...] |
/external/clang/lib/CodeGen/ |
CGExpr.cpp | [all...] |